ROLE BASED CACHE COHERENCE BUS TRAFFIC CONTROL

ROLE BASED CACHE COHERENCE BUS TRAFFIC CONTROL

A method for controlling cache snoop and/or invalidate coherence traffic for specific caches based on transaction attributes is described. A memory management unit (MMU) determines one or more transaction attributes for a cache coherence transaction from a requesting processor. A routing module iden...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: Subramaniam GANASAN Jaya Prakash, BOSTLEY, III Phil Joseph
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator Subramaniam GANASAN Jaya Prakash
BOSTLEY, III Phil Joseph
description A method for controlling cache snoop and/or invalidate coherence traffic for specific caches based on transaction attributes is described. A memory management unit (MMU) determines one or more transaction attributes for a cache coherence transaction from a requesting processor. A routing module identifies a cachability domain and/or shareability domain based on the transaction attributes and routes the cache coherence transaction to one or more caches in the cachability domain and/or shareability domain. Instead of coherence traffic being routed to all caches on a coherence bus, coherence traffic is selectively routed based on transaction attributes such as an address space identifier (ASID), a virtual machine identifier (VMID), a secure bit (NS), a hypervisor identifier (HYP), etc.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2016246721A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2016246721A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2016246721A13</originalsourceid><addsrcrecordid>eNrjZNAL8vdxVXByDHZ1UXB2dPZwVXD293ANcvVzBoqGBiuEBDm6uXk6A0X9QoBKeRhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGhmZGJmbmRoaOhMXGqAEYSJkI</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>ROLE BASED CACHE COHERENCE BUS TRAFFIC CONTROL</title><source>esp@cenet</source><creator>Subramaniam GANASAN Jaya Prakash ; BOSTLEY, III Phil Joseph</creator><creatorcontrib>Subramaniam GANASAN Jaya Prakash ; BOSTLEY, III Phil Joseph</creatorcontrib><description>A method for controlling cache snoop and/or invalidate coherence traffic for specific caches based on transaction attributes is described. A memory management unit (MMU) determines one or more transaction attributes for a cache coherence transaction from a requesting processor. A routing module identifies a cachability domain and/or shareability domain based on the transaction attributes and routes the cache coherence transaction to one or more caches in the cachability domain and/or shareability domain. Instead of coherence traffic being routed to all caches on a coherence bus, coherence traffic is selectively routed based on transaction attributes such as an address space identifier (ASID), a virtual machine identifier (VMID), a secure bit (NS), a hypervisor identifier (HYP), etc.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160825&amp;DB=EPODOC&amp;CC=US&amp;NR=2016246721A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20160825&amp;DB=EPODOC&amp;CC=US&amp;NR=2016246721A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>Subramaniam GANASAN Jaya Prakash</creatorcontrib><creatorcontrib>BOSTLEY, III Phil Joseph</creatorcontrib><title>ROLE BASED CACHE COHERENCE BUS TRAFFIC CONTROL</title><description>A method for controlling cache snoop and/or invalidate coherence traffic for specific caches based on transaction attributes is described. A memory management unit (MMU) determines one or more transaction attributes for a cache coherence transaction from a requesting processor. A routing module identifies a cachability domain and/or shareability domain based on the transaction attributes and routes the cache coherence transaction to one or more caches in the cachability domain and/or shareability domain. Instead of coherence traffic being routed to all caches on a coherence bus, coherence traffic is selectively routed based on transaction attributes such as an address space identifier (ASID), a virtual machine identifier (VMID), a secure bit (NS), a hypervisor identifier (HYP), etc.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAL8vdxVXByDHZ1UXB2dPZwVXD293ANcvVzBoqGBiuEBDm6uXk6A0X9QoBKeRhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGhmZGJmbmRoaOhMXGqAEYSJkI</recordid><startdate>20160825</startdate><enddate>20160825</enddate><creator>Subramaniam GANASAN Jaya Prakash</creator><creator>BOSTLEY, III Phil Joseph</creator><scope>EVB</scope></search><sort><creationdate>20160825</creationdate><title>ROLE BASED CACHE COHERENCE BUS TRAFFIC CONTROL</title><author>Subramaniam GANASAN Jaya Prakash ; BOSTLEY, III Phil Joseph</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2016246721A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>Subramaniam GANASAN Jaya Prakash</creatorcontrib><creatorcontrib>BOSTLEY, III Phil Joseph</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>Subramaniam GANASAN Jaya Prakash</au><au>BOSTLEY, III Phil Joseph</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>ROLE BASED CACHE COHERENCE BUS TRAFFIC CONTROL</title><date>2016-08-25</date><risdate>2016</risdate><abstract>A method for controlling cache snoop and/or invalidate coherence traffic for specific caches based on transaction attributes is described. A memory management unit (MMU) determines one or more transaction attributes for a cache coherence transaction from a requesting processor. A routing module identifies a cachability domain and/or shareability domain based on the transaction attributes and routes the cache coherence transaction to one or more caches in the cachability domain and/or shareability domain. Instead of coherence traffic being routed to all caches on a coherence bus, coherence traffic is selectively routed based on transaction attributes such as an address space identifier (ASID), a virtual machine identifier (VMID), a secure bit (NS), a hypervisor identifier (HYP), etc.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2016246721A1
source esp@cenet
subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title ROLE BASED CACHE COHERENCE BUS TRAFFIC CONTROL
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-15T19%3A12%3A06IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=Subramaniam%20GANASAN%20Jaya%20Prakash&rft.date=2016-08-25&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2016246721A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true