LAMINATED CHIP AND LAMINATED CHIP MANUFACTURING METHOD

LAMINATED CHIP AND LAMINATED CHIP MANUFACTURING METHOD

A laminated chip includes: a first chip; a first wiring layer formed on the first chip; a second chip; a second wiring layer formed on the second chip; and a layer disposed between the first wiring layer and the second wiring layer, the layer includes an adhesive agent configured to bond the first w...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: SUWADA MAKOTO, KAINUMA NORIO, KANDA TAKASHI, BABA SHUNJI
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
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Beschreibung
Zusammenfassung:A laminated chip includes: a first chip; a first wiring layer formed on the first chip; a second chip; a second wiring layer formed on the second chip; and a layer disposed between the first wiring layer and the second wiring layer, the layer includes an adhesive agent configured to bond the first wiring layer and the second wiring layer; a plurality of first bumps connected to the first wiring layer; a plurality of second bumps connected to the second wiring layer; and solder connected to the plurality of first bumps and the plurality of second bumps.