SEMICONDUCTOR DEVICES HAVING SILICIDE AND METHODS OF MANUFACTURING THE SAME
Semiconductor devices, having dual silicides, include a first fin, having N-type impurities, and a second fin, having P-type impurities, on a substrate. A first gate electrode and a first source/drain area are on the first fin. A second gate electrode and a second source/drain area are on the second...
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creator | HSU WEI-HUA LEE HYUNGJONG LEE CHOONGHO YOU JUNGGUN |
description | Semiconductor devices, having dual silicides, include a first fin, having N-type impurities, and a second fin, having P-type impurities, on a substrate. A first gate electrode and a first source/drain area are on the first fin. A second gate electrode and a second source/drain area are on the second fin. An etch stop layer is on the first source/drain area and the second source/drain area. An insulating layer is on the etch stop layer. A first plug connected to the first source/drain area and a second plug connected to the second source/drain area are formed through the insulating layer and the etch stop layer. A first metal silicide layer is in the first source/drain area. A second metal silicide layer having a material different from the first metal silicide layer and having a thickness smaller than the first metal silicide layer is in the second source/drain area. |
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fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2016197074A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2016197074A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2016197074A13</originalsourceid><addsrcrecordid>eNqNyrEKwjAQANAsDqL-w4Gz0KhYOh7J1RyaBHpJ11IkTqKF-v-I4Ac4veUt1UXIs4nBZpNiB5Z6NiTgsOdwBuErG7YEGCx4Si5agdiCx5BbNCl335UcgaCntVrcx8dcNj9XattSMm5XptdQ5mm8lWd5D1n2lT7ppq7qI-rDf-sDQDkujA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR DEVICES HAVING SILICIDE AND METHODS OF MANUFACTURING THE SAME</title><source>esp@cenet</source><creator>HSU WEI-HUA ; LEE HYUNGJONG ; LEE CHOONGHO ; YOU JUNGGUN</creator><creatorcontrib>HSU WEI-HUA ; LEE HYUNGJONG ; LEE CHOONGHO ; YOU JUNGGUN</creatorcontrib><description>Semiconductor devices, having dual silicides, include a first fin, having N-type impurities, and a second fin, having P-type impurities, on a substrate. A first gate electrode and a first source/drain area are on the first fin. A second gate electrode and a second source/drain area are on the second fin. An etch stop layer is on the first source/drain area and the second source/drain area. An insulating layer is on the etch stop layer. A first plug connected to the first source/drain area and a second plug connected to the second source/drain area are formed through the insulating layer and the etch stop layer. A first metal silicide layer is in the first source/drain area. A second metal silicide layer having a material different from the first metal silicide layer and having a thickness smaller than the first metal silicide layer is in the second source/drain area.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160707&DB=EPODOC&CC=US&NR=2016197074A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160707&DB=EPODOC&CC=US&NR=2016197074A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HSU WEI-HUA</creatorcontrib><creatorcontrib>LEE HYUNGJONG</creatorcontrib><creatorcontrib>LEE CHOONGHO</creatorcontrib><creatorcontrib>YOU JUNGGUN</creatorcontrib><title>SEMICONDUCTOR DEVICES HAVING SILICIDE AND METHODS OF MANUFACTURING THE SAME</title><description>Semiconductor devices, having dual silicides, include a first fin, having N-type impurities, and a second fin, having P-type impurities, on a substrate. A first gate electrode and a first source/drain area are on the first fin. A second gate electrode and a second source/drain area are on the second fin. An etch stop layer is on the first source/drain area and the second source/drain area. An insulating layer is on the etch stop layer. A first plug connected to the first source/drain area and a second plug connected to the second source/drain area are formed through the insulating layer and the etch stop layer. A first metal silicide layer is in the first source/drain area. A second metal silicide layer having a material different from the first metal silicide layer and having a thickness smaller than the first metal silicide layer is in the second source/drain area.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwjAQANAsDqL-w4Gz0KhYOh7J1RyaBHpJ11IkTqKF-v-I4Ac4veUt1UXIs4nBZpNiB5Z6NiTgsOdwBuErG7YEGCx4Si5agdiCx5BbNCl335UcgaCntVrcx8dcNj9XattSMm5XptdQ5mm8lWd5D1n2lT7ppq7qI-rDf-sDQDkujA</recordid><startdate>20160707</startdate><enddate>20160707</enddate><creator>HSU WEI-HUA</creator><creator>LEE HYUNGJONG</creator><creator>LEE CHOONGHO</creator><creator>YOU JUNGGUN</creator><scope>EVB</scope></search><sort><creationdate>20160707</creationdate><title>SEMICONDUCTOR DEVICES HAVING SILICIDE AND METHODS OF MANUFACTURING THE SAME</title><author>HSU WEI-HUA ; LEE HYUNGJONG ; LEE CHOONGHO ; YOU JUNGGUN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2016197074A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HSU WEI-HUA</creatorcontrib><creatorcontrib>LEE HYUNGJONG</creatorcontrib><creatorcontrib>LEE CHOONGHO</creatorcontrib><creatorcontrib>YOU JUNGGUN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HSU WEI-HUA</au><au>LEE HYUNGJONG</au><au>LEE CHOONGHO</au><au>YOU JUNGGUN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR DEVICES HAVING SILICIDE AND METHODS OF MANUFACTURING THE SAME</title><date>2016-07-07</date><risdate>2016</risdate><abstract>Semiconductor devices, having dual silicides, include a first fin, having N-type impurities, and a second fin, having P-type impurities, on a substrate. A first gate electrode and a first source/drain area are on the first fin. A second gate electrode and a second source/drain area are on the second fin. An etch stop layer is on the first source/drain area and the second source/drain area. An insulating layer is on the etch stop layer. A first plug connected to the first source/drain area and a second plug connected to the second source/drain area are formed through the insulating layer and the etch stop layer. A first metal silicide layer is in the first source/drain area. A second metal silicide layer having a material different from the first metal silicide layer and having a thickness smaller than the first metal silicide layer is in the second source/drain area.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | SEMICONDUCTOR DEVICES HAVING SILICIDE AND METHODS OF MANUFACTURING THE SAME |
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