DIGITAL PHASE CONTROLLED DELAY CIRCUIT
An adjustable phase clock generator circuit is described that may include a DLL and a phase adjustor to further adjust the phase of a selected clock phase from the DLL. Both the DLL and phase adjustor may be formed from current starved delay elements that are biased from a common bias generator circ...
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| creator | BANGS HANS JOAKIM HACKNEY PHILIP SUETINOV VIACHESLAV |
| description | An adjustable phase clock generator circuit is described that may include a DLL and a phase adjustor to further adjust the phase of a selected clock phase from the DLL. Both the DLL and phase adjustor may be formed from current starved delay elements that are biased from a common bias generator circuit. |
| format | Patent |
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| subjects | AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY ELECTRICITY INFORMATION STORAGE PHYSICS STATIC STORES |
| title | DIGITAL PHASE CONTROLLED DELAY CIRCUIT |
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