STRUCTURE AND METHOD TO MINIMIZE WARPAGE OF PACKAGED SEMICONDUCTOR DEVICES
A packaged semiconductor device includes a substrate, an electronic device coupled to the substrate, encapsulant including a first major surface surrounding the electronic device, and an oxygen barrier layer within fifty percent of a thickness of the encapsulant from a second major surface of the en...
Gespeichert in:
Hauptverfasser: | , , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | MATHEW VARUGHESE SINGH AKHILESH K GUAJARDO JAMES R LAKHERA NISHANT |
description | A packaged semiconductor device includes a substrate, an electronic device coupled to the substrate, encapsulant including a first major surface surrounding the electronic device, and an oxygen barrier layer within fifty percent of a thickness of the encapsulant from a second major surface of the encapsulant. The oxygen barrier covers at least a portion of an area of the second major surface of the encapsulant to help reduce or eliminate warping of the encapsulant and/or the substrate of the packaged semiconductor device due to oxidation. A thickness of the oxygen barrier layer is less than 100 microns. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2016064299A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2016064299A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2016064299A13</originalsourceid><addsrcrecordid>eNrjZPAKDgkKdQ4JDXJVcPRzUfB1DfHwd1EI8Vfw9fTz9PWMclUIdwwKcHR3VfB3UwhwdPYGMl0Ugl19PZ39_VyAOv2DFFxcwzydXYN5GFjTEnOKU3mhNDeDsptriLOHbmpBfnxqcUFicmpeakl8aLCRgaGZgZmJkaWlo6ExcaoAHTIuaw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>STRUCTURE AND METHOD TO MINIMIZE WARPAGE OF PACKAGED SEMICONDUCTOR DEVICES</title><source>esp@cenet</source><creator>MATHEW VARUGHESE ; SINGH AKHILESH K ; GUAJARDO JAMES R ; LAKHERA NISHANT</creator><creatorcontrib>MATHEW VARUGHESE ; SINGH AKHILESH K ; GUAJARDO JAMES R ; LAKHERA NISHANT</creatorcontrib><description>A packaged semiconductor device includes a substrate, an electronic device coupled to the substrate, encapsulant including a first major surface surrounding the electronic device, and an oxygen barrier layer within fifty percent of a thickness of the encapsulant from a second major surface of the encapsulant. The oxygen barrier covers at least a portion of an area of the second major surface of the encapsulant to help reduce or eliminate warping of the encapsulant and/or the substrate of the packaged semiconductor device due to oxidation. A thickness of the oxygen barrier layer is less than 100 microns.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2016</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160303&DB=EPODOC&CC=US&NR=2016064299A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25547,76298</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20160303&DB=EPODOC&CC=US&NR=2016064299A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MATHEW VARUGHESE</creatorcontrib><creatorcontrib>SINGH AKHILESH K</creatorcontrib><creatorcontrib>GUAJARDO JAMES R</creatorcontrib><creatorcontrib>LAKHERA NISHANT</creatorcontrib><title>STRUCTURE AND METHOD TO MINIMIZE WARPAGE OF PACKAGED SEMICONDUCTOR DEVICES</title><description>A packaged semiconductor device includes a substrate, an electronic device coupled to the substrate, encapsulant including a first major surface surrounding the electronic device, and an oxygen barrier layer within fifty percent of a thickness of the encapsulant from a second major surface of the encapsulant. The oxygen barrier covers at least a portion of an area of the second major surface of the encapsulant to help reduce or eliminate warping of the encapsulant and/or the substrate of the packaged semiconductor device due to oxidation. A thickness of the oxygen barrier layer is less than 100 microns.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2016</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPAKDgkKdQ4JDXJVcPRzUfB1DfHwd1EI8Vfw9fTz9PWMclUIdwwKcHR3VfB3UwhwdPYGMl0Ugl19PZ39_VyAOv2DFFxcwzydXYN5GFjTEnOKU3mhNDeDsptriLOHbmpBfnxqcUFicmpeakl8aLCRgaGZgZmJkaWlo6ExcaoAHTIuaw</recordid><startdate>20160303</startdate><enddate>20160303</enddate><creator>MATHEW VARUGHESE</creator><creator>SINGH AKHILESH K</creator><creator>GUAJARDO JAMES R</creator><creator>LAKHERA NISHANT</creator><scope>EVB</scope></search><sort><creationdate>20160303</creationdate><title>STRUCTURE AND METHOD TO MINIMIZE WARPAGE OF PACKAGED SEMICONDUCTOR DEVICES</title><author>MATHEW VARUGHESE ; SINGH AKHILESH K ; GUAJARDO JAMES R ; LAKHERA NISHANT</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2016064299A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2016</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>MATHEW VARUGHESE</creatorcontrib><creatorcontrib>SINGH AKHILESH K</creatorcontrib><creatorcontrib>GUAJARDO JAMES R</creatorcontrib><creatorcontrib>LAKHERA NISHANT</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MATHEW VARUGHESE</au><au>SINGH AKHILESH K</au><au>GUAJARDO JAMES R</au><au>LAKHERA NISHANT</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>STRUCTURE AND METHOD TO MINIMIZE WARPAGE OF PACKAGED SEMICONDUCTOR DEVICES</title><date>2016-03-03</date><risdate>2016</risdate><abstract>A packaged semiconductor device includes a substrate, an electronic device coupled to the substrate, encapsulant including a first major surface surrounding the electronic device, and an oxygen barrier layer within fifty percent of a thickness of the encapsulant from a second major surface of the encapsulant. The oxygen barrier covers at least a portion of an area of the second major surface of the encapsulant to help reduce or eliminate warping of the encapsulant and/or the substrate of the packaged semiconductor device due to oxidation. A thickness of the oxygen barrier layer is less than 100 microns.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2016064299A1 |
source | esp@cenet |
subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
title | STRUCTURE AND METHOD TO MINIMIZE WARPAGE OF PACKAGED SEMICONDUCTOR DEVICES |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-17T00%3A38%3A30IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MATHEW%20VARUGHESE&rft.date=2016-03-03&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2016064299A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |