SEMICONDUCTOR DEVICE

In a memory cell array region and a source contact region defined in a surface of a semiconductor substrate, a memory cell transistor including a floating gate electrode and a control gate electrode is formed. In a gate contact region, a dummy floating gate electrode is arranged to partially be supe...

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Bibliographische Detailangaben
1. Verfasser: ISHIGAKI YOSHIYUKI
Format: Patent
Sprache:eng
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