SEMICONDUCTOR MEMORY DEVICE
A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a...
Gespeichert in:
Hauptverfasser: | , , |
---|---|
Format: | Patent |
Sprache: | eng |
Schlagworte: | |
Online-Zugang: | Volltext bestellen |
Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
container_end_page | |
---|---|
container_issue | |
container_start_page | |
container_title | |
container_volume | |
creator | CHOI BYEONGAN LEE DOOAN NA ONE-GYUN |
description | A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality of repair cell line selection units suitable for selecting the plurality of repair cell lines, respectively, in place of normal cell line selection units corresponding to fail information of the local address; a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal cell line selection units corresponding to the fail information, and enabling normal cell line selection units unrelated to the fail information; and an address determination unit suitable for controlling the plurality of repair cell line selection units based on the fail information. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2015098286A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2015098286A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2015098286A13</originalsourceid><addsrcrecordid>eNrjZJAOdvX1dPb3cwl1DvEPUvB19fUPilRwcQ3zdHblYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBoamBpYWRhZmjobGxKkCAOhgIbA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SEMICONDUCTOR MEMORY DEVICE</title><source>esp@cenet</source><creator>CHOI BYEONGAN ; LEE DOOAN ; NA ONE-GYUN</creator><creatorcontrib>CHOI BYEONGAN ; LEE DOOAN ; NA ONE-GYUN</creatorcontrib><description>A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality of repair cell line selection units suitable for selecting the plurality of repair cell lines, respectively, in place of normal cell line selection units corresponding to fail information of the local address; a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal cell line selection units corresponding to the fail information, and enabling normal cell line selection units unrelated to the fail information; and an address determination unit suitable for controlling the plurality of repair cell line selection units based on the fail information.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150409&DB=EPODOC&CC=US&NR=2015098286A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150409&DB=EPODOC&CC=US&NR=2015098286A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHOI BYEONGAN</creatorcontrib><creatorcontrib>LEE DOOAN</creatorcontrib><creatorcontrib>NA ONE-GYUN</creatorcontrib><title>SEMICONDUCTOR MEMORY DEVICE</title><description>A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality of repair cell line selection units suitable for selecting the plurality of repair cell lines, respectively, in place of normal cell line selection units corresponding to fail information of the local address; a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal cell line selection units corresponding to the fail information, and enabling normal cell line selection units unrelated to the fail information; and an address determination unit suitable for controlling the plurality of repair cell line selection units based on the fail information.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZJAOdvX1dPb3cwl1DvEPUvB19fUPilRwcQ3zdHblYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBoamBpYWRhZmjobGxKkCAOhgIbA</recordid><startdate>20150409</startdate><enddate>20150409</enddate><creator>CHOI BYEONGAN</creator><creator>LEE DOOAN</creator><creator>NA ONE-GYUN</creator><scope>EVB</scope></search><sort><creationdate>20150409</creationdate><title>SEMICONDUCTOR MEMORY DEVICE</title><author>CHOI BYEONGAN ; LEE DOOAN ; NA ONE-GYUN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2015098286A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHOI BYEONGAN</creatorcontrib><creatorcontrib>LEE DOOAN</creatorcontrib><creatorcontrib>NA ONE-GYUN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHOI BYEONGAN</au><au>LEE DOOAN</au><au>NA ONE-GYUN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SEMICONDUCTOR MEMORY DEVICE</title><date>2015-04-09</date><risdate>2015</risdate><abstract>A semiconductor memory device includes: a memory cell array region having a plurality of normal cell lines and a plurality of repair cell lines; a plurality of normal cell line selection units suitable for selecting the plurality of normal cell lines, respectively, in response to a local address; a plurality of repair cell line selection units suitable for selecting the plurality of repair cell lines, respectively, in place of normal cell line selection units corresponding to fail information of the local address; a fuse driving unit comprising a fuse array in which the fail information is programmed, suitable for disabling the normal cell line selection units corresponding to the fail information, and enabling normal cell line selection units unrelated to the fail information; and an address determination unit suitable for controlling the plurality of repair cell line selection units based on the fail information.</abstract><oa>free_for_read</oa></addata></record> |
fulltext | fulltext_linktorsrc |
identifier | |
ispartof | |
issn | |
language | eng |
recordid | cdi_epo_espacenet_US2015098286A1 |
source | esp@cenet |
subjects | INFORMATION STORAGE PHYSICS STATIC STORES |
title | SEMICONDUCTOR MEMORY DEVICE |
url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-30T03%3A33%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHOI%20BYEONGAN&rft.date=2015-04-09&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2015098286A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |