PSEUDO-ERROR GENERATING DEVICE

PSEUDO-ERROR GENERATING DEVICE

A pseudo-error generating device of an embodiment includes error injection information including a header section and a data section, a storage section configured to store the error injection information, and at least one error injecting circuit, connected to a test target circuit through a predeter...

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1. Verfasser: UNESAKI TSUTOMU
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator UNESAKI TSUTOMU
description A pseudo-error generating device of an embodiment includes error injection information including a header section and a data section, a storage section configured to store the error injection information, and at least one error injecting circuit, connected to a test target circuit through a predetermined path, configured to inject a pseudo-error to the predetermined path. The header section includes a port specifying one of the at least one error injecting circuit, and an address specifying the data section. The data section includes an injection condition and error injection data for injecting the pseudo-error. The error injecting circuit injects the pseudo-error to the predetermined path based on the injection condition and the error injection data.
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The header section includes a port specifying one of the at least one error injecting circuit, and an address specifying the data section. The data section includes an injection condition and error injection data for injecting the pseudo-error. The error injecting circuit injects the pseudo-error to the predetermined path based on the injection condition and the error injection data.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20150312&amp;DB=EPODOC&amp;CC=US&amp;NR=2015074473A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,778,883,25551,76302</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20150312&amp;DB=EPODOC&amp;CC=US&amp;NR=2015074473A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>UNESAKI TSUTOMU</creatorcontrib><title>PSEUDO-ERROR GENERATING DEVICE</title><description>A pseudo-error generating device of an embodiment includes error injection information including a header section and a data section, a storage section configured to store the error injection information, and at least one error injecting circuit, connected to a test target circuit through a predetermined path, configured to inject a pseudo-error to the predetermined path. The header section includes a port specifying one of the at least one error injecting circuit, and an address specifying the data section. The data section includes an injection condition and error injection data for injecting the pseudo-error. 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The header section includes a port specifying one of the at least one error injecting circuit, and an address specifying the data section. The data section includes an injection condition and error injection data for injecting the pseudo-error. The error injecting circuit injects the pseudo-error to the predetermined path based on the injection condition and the error injection data.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title PSEUDO-ERROR GENERATING DEVICE
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