LOW POWER DIGITAL FRACTIONAL DIVIDER WITH GLITCHLESS OUTPUT

LOW POWER DIGITAL FRACTIONAL DIVIDER WITH GLITCHLESS OUTPUT

A digital circuit that divides a high speed digital clock by a fractional value is described. The circuit utilizes a divider circuit and shifts the divider clock by a fraction of a phase to achieve the desired fractional division. A clock mux is used to perform the clock shift, and a masking mux is...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: YOKOYAMA-MARTIN DAVID A, WOLFER SKYE
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRONIC CIRCUITRY
ELECTRIC COMMUNICATION TECHNIQUE
ELECTRICITY
PULSE TECHNIQUE
TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHICCOMMUNICATION
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Beschreibung
Zusammenfassung:A digital circuit that divides a high speed digital clock by a fractional value is described. The circuit utilizes a divider circuit and shifts the divider clock by a fraction of a phase to achieve the desired fractional division. A clock mux is used to perform the clock shift, and a masking mux is used to eliminate glitches during the clock shift.