SYSTEM AND METHOD FOR IDLE STATE OPTIMIZATION IN A MULTI-PROCESSOR SYSTEM ON A CHIP
Various embodiments of methods and systems for idle state optimization in a portable computing device ("PCD") are disclosed. An exemplary method includes comparing an aggregate power consumption level for all processing cores in the PCD to a power budget and, if there is available headroom...
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | JAIN ANKUR BEGIN HENRI MITTER VINAY VADAKKANMARUVEEDU UNNIKRISHNAN CHIDAMBARAM PRAVEEN |
| description | Various embodiments of methods and systems for idle state optimization in a portable computing device ("PCD") are disclosed. An exemplary method includes comparing an aggregate power consumption level for all processing cores in the PCD to a power budget and, if there is available headroom in the power budget, transitioning cores operating in a first idle state to a different idle state. In doing so, the latency value associated with bringing the transitioned cores out of an idle state and into an active state, should the need arise, may be reduced. The result is that user experience and QoS may be improved as an otherwise idle core in an idle state with a long latency time may be better positioned to quickly transition to an active state and process a workload. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2015026495A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2015026495A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2015026495A13</originalsourceid><addsrcrecordid>eNrjZAgOjgwOcfVVcPRzUfB1DfHwd1Fw8w9S8HTxcVUIDnEMcVXwDwjx9PWMcgzx9PdT8PRTcFTwDfUJ8dQNCPJ3dg0OBiqGGuEPknP28AzgYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBoamBkZmJpamjobGxKkCALGsMK8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SYSTEM AND METHOD FOR IDLE STATE OPTIMIZATION IN A MULTI-PROCESSOR SYSTEM ON A CHIP</title><source>esp@cenet</source><creator>JAIN ANKUR ; BEGIN HENRI ; MITTER VINAY ; VADAKKANMARUVEEDU UNNIKRISHNAN ; CHIDAMBARAM PRAVEEN</creator><creatorcontrib>JAIN ANKUR ; BEGIN HENRI ; MITTER VINAY ; VADAKKANMARUVEEDU UNNIKRISHNAN ; CHIDAMBARAM PRAVEEN</creatorcontrib><description>Various embodiments of methods and systems for idle state optimization in a portable computing device ("PCD") are disclosed. An exemplary method includes comparing an aggregate power consumption level for all processing cores in the PCD to a power budget and, if there is available headroom in the power budget, transitioning cores operating in a first idle state to a different idle state. In doing so, the latency value associated with bringing the transitioned cores out of an idle state and into an active state, should the need arise, may be reduced. The result is that user experience and QoS may be improved as an otherwise idle core in an idle state with a long latency time may be better positioned to quickly transition to an active state and process a workload.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2015</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150122&DB=EPODOC&CC=US&NR=2015026495A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,309,781,886,25569,76552</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20150122&DB=EPODOC&CC=US&NR=2015026495A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>JAIN ANKUR</creatorcontrib><creatorcontrib>BEGIN HENRI</creatorcontrib><creatorcontrib>MITTER VINAY</creatorcontrib><creatorcontrib>VADAKKANMARUVEEDU UNNIKRISHNAN</creatorcontrib><creatorcontrib>CHIDAMBARAM PRAVEEN</creatorcontrib><title>SYSTEM AND METHOD FOR IDLE STATE OPTIMIZATION IN A MULTI-PROCESSOR SYSTEM ON A CHIP</title><description>Various embodiments of methods and systems for idle state optimization in a portable computing device ("PCD") are disclosed. An exemplary method includes comparing an aggregate power consumption level for all processing cores in the PCD to a power budget and, if there is available headroom in the power budget, transitioning cores operating in a first idle state to a different idle state. In doing so, the latency value associated with bringing the transitioned cores out of an idle state and into an active state, should the need arise, may be reduced. The result is that user experience and QoS may be improved as an otherwise idle core in an idle state with a long latency time may be better positioned to quickly transition to an active state and process a workload.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2015</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZAgOjgwOcfVVcPRzUfB1DfHwd1Fw8w9S8HTxcVUIDnEMcVXwDwjx9PWMcgzx9PdT8PRTcFTwDfUJ8dQNCPJ3dg0OBiqGGuEPknP28AzgYWBNS8wpTuWF0twMym6uIc4euqkF-fGpxQWJyal5qSXxocFGBoamBkZmJpamjobGxKkCALGsMK8</recordid><startdate>20150122</startdate><enddate>20150122</enddate><creator>JAIN ANKUR</creator><creator>BEGIN HENRI</creator><creator>MITTER VINAY</creator><creator>VADAKKANMARUVEEDU UNNIKRISHNAN</creator><creator>CHIDAMBARAM PRAVEEN</creator><scope>EVB</scope></search><sort><creationdate>20150122</creationdate><title>SYSTEM AND METHOD FOR IDLE STATE OPTIMIZATION IN A MULTI-PROCESSOR SYSTEM ON A CHIP</title><author>JAIN ANKUR ; BEGIN HENRI ; MITTER VINAY ; VADAKKANMARUVEEDU UNNIKRISHNAN ; CHIDAMBARAM PRAVEEN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2015026495A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2015</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>JAIN ANKUR</creatorcontrib><creatorcontrib>BEGIN HENRI</creatorcontrib><creatorcontrib>MITTER VINAY</creatorcontrib><creatorcontrib>VADAKKANMARUVEEDU UNNIKRISHNAN</creatorcontrib><creatorcontrib>CHIDAMBARAM PRAVEEN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>JAIN ANKUR</au><au>BEGIN HENRI</au><au>MITTER VINAY</au><au>VADAKKANMARUVEEDU UNNIKRISHNAN</au><au>CHIDAMBARAM PRAVEEN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SYSTEM AND METHOD FOR IDLE STATE OPTIMIZATION IN A MULTI-PROCESSOR SYSTEM ON A CHIP</title><date>2015-01-22</date><risdate>2015</risdate><abstract>Various embodiments of methods and systems for idle state optimization in a portable computing device ("PCD") are disclosed. An exemplary method includes comparing an aggregate power consumption level for all processing cores in the PCD to a power budget and, if there is available headroom in the power budget, transitioning cores operating in a first idle state to a different idle state. In doing so, the latency value associated with bringing the transitioned cores out of an idle state and into an active state, should the need arise, may be reduced. The result is that user experience and QoS may be improved as an otherwise idle core in an idle state with a long latency time may be better positioned to quickly transition to an active state and process a workload.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US2015026495A1 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | SYSTEM AND METHOD FOR IDLE STATE OPTIMIZATION IN A MULTI-PROCESSOR SYSTEM ON A CHIP |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-13T22%3A44%3A29IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=JAIN%20ANKUR&rft.date=2015-01-22&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2015026495A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |