DATA PROCESSING APPARATUS AND METHOD FOR HANDLING RETRIEVAL OF INSTRUCTIONS FROM AN INSTRUCTION CACHE

A data processing apparatus and method are provided for handling retrieval of instructions from an instruction cache. Fetch circuitry retrieves instructions from the instruction cache into a temporary buffer, and execution circuitry executes a sequence of instructions retrieved from the temporary bu...

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1. Verfasser: GREENHALGH PETER RICHARD
Format: Patent
Sprache:eng
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Zusammenfassung:A data processing apparatus and method are provided for handling retrieval of instructions from an instruction cache. Fetch circuitry retrieves instructions from the instruction cache into a temporary buffer, and execution circuitry executes a sequence of instructions retrieved from the temporary buffer, that sequence including branch instructions. Branch prediction circuitry is configured to predict, for each identified branch instruction in the sequence, if that branch instruction will result in a taken branch when that branch instruction is subsequently executed by the execution circuitry. In a normal operating mode, the fetch circuitry retrieves one or more speculative instructions from the instruction cache between the time that a source branch instruction is retrieved from the instruction cache and the branch prediction circuitry predicts if that source branch instruction will result in the taken branch. In the event that that source branch instruction is predicted as taken, the one or more speculative instructions are discarded. In the event that a source branch instruction is predicted as taken, throttle prediction circuitry maintains a count value indicative of a number of instructions appearing in the sequence between that source branch instruction and a subsequent branch instruction in the sequence that is also predicted as taken. Responsive to a subsequent occurrence of the source branch instruction, that is predicted as taken, the throttle prediction circuitry operates the fetch circuitry in a throttled mode where the number of instructions subsequently retrieved by the fetch circuitry from the instruction cache is limited dependent on the count value, and then the fetch circuitry is prevented from retrieving any further instructions from the instruction cache for a predetermined number of clock cycles. This serves to reduce the power consumption consumed in accessing the instruction cache to retrieve speculative instructions which later need to be discarded.