Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips
A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a firs...
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| creator | DENISON MARIE LOPEZ OSVALDO JORGE HERBSOMMER JUAN ALEJANDRO CARPENTER BRIAN ASHLEY NOQUIL JONATHAN |
| description | A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203). |
| format | Patent |
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NOQUIL JONATHAN</creatorcontrib><description>A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; 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LOPEZ OSVALDO JORGE ; HERBSOMMER JUAN ALEJANDRO ; CARPENTER BRIAN ASHLEY ; NOQUIL JONATHAN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2014306332A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2014</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>DENISON MARIE</creatorcontrib><creatorcontrib>LOPEZ OSVALDO JORGE</creatorcontrib><creatorcontrib>HERBSOMMER JUAN ALEJANDRO</creatorcontrib><creatorcontrib>CARPENTER BRIAN ASHLEY</creatorcontrib><creatorcontrib>NOQUIL JONATHAN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>DENISON MARIE</au><au>LOPEZ OSVALDO JORGE</au><au>HERBSOMMER JUAN ALEJANDRO</au><au>CARPENTER BRIAN ASHLEY</au><au>NOQUIL JONATHAN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips</title><date>2014-10-16</date><risdate>2014</risdate><abstract>A packaged multi-output converter (200) comprising a leadframe with a chip pad (201) as ground terminal and a plurality of leads (202) including the electrical input terminal (203); a first FET chip (sync chip, 220) with its source terminal affixed to the leadframe and on its opposite surface a first drain terminal (221) positioned adjacent to a second drain terminal (222), the drain terminals connected respectively by a first (241) and a second (242) metal clip to a first (204) and second (205) output lead; a second FET chip (control chip, 211), positioned vertically over the first drain terminal, with its source terminal attached onto the first clip; a third FET chip (control chip, 212), positioned vertically over the second drain terminal, with its source terminal attached onto the second clip; and the drain terminals (213, 214) of the second and third chips attached onto a third metal clip (260) connected to the input lead (203).</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES |
| title | Integrating Multi-Output Power Converters Having Vertically Stacked Semiconductor Chips |
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