ANTI-TAMPER SYSTEM BASED ON DUAL RANDOM BITS GENERATORS FOR INTEGRATED CIRCUITS

An apparatus includes a mesh block, a first number generator configured to generate a first number, a second number generator configured to generate a second number, and a comparator block configured to compare the first number with the second number and generate an output signal from the mesh block...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	A/L KRISHNASAMY RAJ KUMAR, THUM CHIA CHIEH, LEE MOO KIT
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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