TECHNIQUES FOR ENHANCING FRACTURE RESISTANCE OF INTERCONNECTS

Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In...

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Hauptverfasser: BHINGARDE SIDDHARTH B, KOBRINSKY MAURO J, PANTUSO DANIEL, O'DAY MICHAEL P, JEZEWSKI CHRISTOPHER J
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creator BHINGARDE SIDDHARTH B
KOBRINSKY MAURO J
PANTUSO DANIEL
O'DAY MICHAEL P
JEZEWSKI CHRISTOPHER J
description Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2014210098A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2014210098A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2014210098A13</originalsourceid><addsrcrecordid>eNrjZLANcXX28PMMDHUNVnDzD1Jw9fNw9HP29HNXcAtydA4JDXJVCHIN9gwOAYq6Kvi7KXj6hbgGOfv7-bk6hwTzMLCmJeYUp_JCaW4GZTfXEGcP3dSC_PjU4oLE5NS81JL40GAjA0MTI0MDA0sLR0Nj4lQBAPDTKvo</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>TECHNIQUES FOR ENHANCING FRACTURE RESISTANCE OF INTERCONNECTS</title><source>esp@cenet</source><creator>BHINGARDE SIDDHARTH B ; KOBRINSKY MAURO J ; PANTUSO DANIEL ; O'DAY MICHAEL P ; JEZEWSKI CHRISTOPHER J</creator><creatorcontrib>BHINGARDE SIDDHARTH B ; KOBRINSKY MAURO J ; PANTUSO DANIEL ; O'DAY MICHAEL P ; JEZEWSKI CHRISTOPHER J</creatorcontrib><description>Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20140731&amp;DB=EPODOC&amp;CC=US&amp;NR=2014210098A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20140731&amp;DB=EPODOC&amp;CC=US&amp;NR=2014210098A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>BHINGARDE SIDDHARTH B</creatorcontrib><creatorcontrib>KOBRINSKY MAURO J</creatorcontrib><creatorcontrib>PANTUSO DANIEL</creatorcontrib><creatorcontrib>O'DAY MICHAEL P</creatorcontrib><creatorcontrib>JEZEWSKI CHRISTOPHER J</creatorcontrib><title>TECHNIQUES FOR ENHANCING FRACTURE RESISTANCE OF INTERCONNECTS</title><description>Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2014</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLANcXX28PMMDHUNVnDzD1Jw9fNw9HP29HNXcAtydA4JDXJVCHIN9gwOAYq6Kvi7KXj6hbgGOfv7-bk6hwTzMLCmJeYUp_JCaW4GZTfXEGcP3dSC_PjU4oLE5NS81JL40GAjA0MTI0MDA0sLR0Nj4lQBAPDTKvo</recordid><startdate>20140731</startdate><enddate>20140731</enddate><creator>BHINGARDE SIDDHARTH B</creator><creator>KOBRINSKY MAURO J</creator><creator>PANTUSO DANIEL</creator><creator>O'DAY MICHAEL P</creator><creator>JEZEWSKI CHRISTOPHER J</creator><scope>EVB</scope></search><sort><creationdate>20140731</creationdate><title>TECHNIQUES FOR ENHANCING FRACTURE RESISTANCE OF INTERCONNECTS</title><author>BHINGARDE SIDDHARTH B ; KOBRINSKY MAURO J ; PANTUSO DANIEL ; O'DAY MICHAEL P ; JEZEWSKI CHRISTOPHER J</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2014210098A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2014</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>BHINGARDE SIDDHARTH B</creatorcontrib><creatorcontrib>KOBRINSKY MAURO J</creatorcontrib><creatorcontrib>PANTUSO DANIEL</creatorcontrib><creatorcontrib>O'DAY MICHAEL P</creatorcontrib><creatorcontrib>JEZEWSKI CHRISTOPHER J</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>BHINGARDE SIDDHARTH B</au><au>KOBRINSKY MAURO J</au><au>PANTUSO DANIEL</au><au>O'DAY MICHAEL P</au><au>JEZEWSKI CHRISTOPHER J</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>TECHNIQUES FOR ENHANCING FRACTURE RESISTANCE OF INTERCONNECTS</title><date>2014-07-31</date><risdate>2014</risdate><abstract>Techniques and structure are disclosed for enhancing fracture resistance of back-end interconnects and other such interconnect structures by increasing via density. Increased via density can be provided, for example, within the filler/dummified portion(s) of adjacent circuit layers within a die. In some cases, an electrically isolated (floating) filler line of an upper circuit layer may include a via which lands on a floating filler line of a lower circuit layer in a region corresponding to where the filler lines cross/intersect. In some such cases, the floating filler line of the upper circuit layer may be formed as a dual-damascene structure including such a via. In some embodiments, a via similarly may be provided between a floating filler line of the upper circuit layer and a sufficiently electrically isolated interconnect line of the lower circuit layer. The techniques/structure can be used to provide mechanical integrity for the die.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title TECHNIQUES FOR ENHANCING FRACTURE RESISTANCE OF INTERCONNECTS
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-27T14%3A40%3A45IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=BHINGARDE%20SIDDHARTH%20B&rft.date=2014-07-31&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2014210098A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true