MEMORY CIRCUITRY INCLUDING COMPUTATIONAL CIRCUITRY FOR PERFORMING SUPPLEMENTAL FUNCTIONS

A computer system includes but is not limited to a primary processing circuitry, a bus coupled to the primary processing circuitry, and memory circuitry coupled to the bus. The memory circuitry is physically separated from the primary processing circuitry. The memory circuitry includes at least one...

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Hauptverfasser: HYDE RODERICK A, PASCH NICHOLAS F, TEGREENE CLARENCE T
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Sprache:eng
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creator HYDE RODERICK A
PASCH NICHOLAS F
TEGREENE CLARENCE T
description A computer system includes but is not limited to a primary processing circuitry, a bus coupled to the primary processing circuitry, and memory circuitry coupled to the bus. The memory circuitry is physically separated from the primary processing circuitry. The memory circuitry includes at least one integrated memory circuit and computational circuitry. The at least one integrated memory circuit configured to store and retrieve data and to provide to the bus, during accessing intervals, requested data for the primary processing circuitry. The computational circuitry co-located with the at least one integrated memory circuit, the computational circuitry co-located with integrated memory circuit can be configured for performing supplemental functions at least partially during time periods that are not accessing intervals.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2014208041A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2014208041A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2014208041A13</originalsourceid><addsrcrecordid>eNrjZIjwdfX1D4pUcPYMcg71DAGyPP2cfUJdPP3cFZz9fQNCQxxDPP39HH2QVLj5BykEuAYBKV-QsuDQgAAfV19XvxCgKrdQP2eQhmAeBta0xJziVF4ozc2g7OYa4uyhm1qQH59aXJCYnJqXWhIfGmxkYGhiZGBhYGLoaGhMnCoAQOYzJA</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>MEMORY CIRCUITRY INCLUDING COMPUTATIONAL CIRCUITRY FOR PERFORMING SUPPLEMENTAL FUNCTIONS</title><source>esp@cenet</source><creator>HYDE RODERICK A ; PASCH NICHOLAS F ; TEGREENE CLARENCE T</creator><creatorcontrib>HYDE RODERICK A ; PASCH NICHOLAS F ; TEGREENE CLARENCE T</creatorcontrib><description>A computer system includes but is not limited to a primary processing circuitry, a bus coupled to the primary processing circuitry, and memory circuitry coupled to the bus. The memory circuitry is physically separated from the primary processing circuitry. The memory circuitry includes at least one integrated memory circuit and computational circuitry. The at least one integrated memory circuit configured to store and retrieve data and to provide to the bus, during accessing intervals, requested data for the primary processing circuitry. The computational circuitry co-located with the at least one integrated memory circuit, the computational circuitry co-located with integrated memory circuit can be configured for performing supplemental functions at least partially during time periods that are not accessing intervals.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20140724&amp;DB=EPODOC&amp;CC=US&amp;NR=2014208041A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20140724&amp;DB=EPODOC&amp;CC=US&amp;NR=2014208041A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HYDE RODERICK A</creatorcontrib><creatorcontrib>PASCH NICHOLAS F</creatorcontrib><creatorcontrib>TEGREENE CLARENCE T</creatorcontrib><title>MEMORY CIRCUITRY INCLUDING COMPUTATIONAL CIRCUITRY FOR PERFORMING SUPPLEMENTAL FUNCTIONS</title><description>A computer system includes but is not limited to a primary processing circuitry, a bus coupled to the primary processing circuitry, and memory circuitry coupled to the bus. The memory circuitry is physically separated from the primary processing circuitry. The memory circuitry includes at least one integrated memory circuit and computational circuitry. The at least one integrated memory circuit configured to store and retrieve data and to provide to the bus, during accessing intervals, requested data for the primary processing circuitry. The computational circuitry co-located with the at least one integrated memory circuit, the computational circuitry co-located with integrated memory circuit can be configured for performing supplemental functions at least partially during time periods that are not accessing intervals.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2014</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZIjwdfX1D4pUcPYMcg71DAGyPP2cfUJdPP3cFZz9fQNCQxxDPP39HH2QVLj5BykEuAYBKV-QsuDQgAAfV19XvxCgKrdQP2eQhmAeBta0xJziVF4ozc2g7OYa4uyhm1qQH59aXJCYnJqXWhIfGmxkYGhiZGBhYGLoaGhMnCoAQOYzJA</recordid><startdate>20140724</startdate><enddate>20140724</enddate><creator>HYDE RODERICK A</creator><creator>PASCH NICHOLAS F</creator><creator>TEGREENE CLARENCE T</creator><scope>EVB</scope></search><sort><creationdate>20140724</creationdate><title>MEMORY CIRCUITRY INCLUDING COMPUTATIONAL CIRCUITRY FOR PERFORMING SUPPLEMENTAL FUNCTIONS</title><author>HYDE RODERICK A ; PASCH NICHOLAS F ; TEGREENE CLARENCE T</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2014208041A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2014</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>HYDE RODERICK A</creatorcontrib><creatorcontrib>PASCH NICHOLAS F</creatorcontrib><creatorcontrib>TEGREENE CLARENCE T</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HYDE RODERICK A</au><au>PASCH NICHOLAS F</au><au>TEGREENE CLARENCE T</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>MEMORY CIRCUITRY INCLUDING COMPUTATIONAL CIRCUITRY FOR PERFORMING SUPPLEMENTAL FUNCTIONS</title><date>2014-07-24</date><risdate>2014</risdate><abstract>A computer system includes but is not limited to a primary processing circuitry, a bus coupled to the primary processing circuitry, and memory circuitry coupled to the bus. The memory circuitry is physically separated from the primary processing circuitry. The memory circuitry includes at least one integrated memory circuit and computational circuitry. The at least one integrated memory circuit configured to store and retrieve data and to provide to the bus, during accessing intervals, requested data for the primary processing circuitry. The computational circuitry co-located with the at least one integrated memory circuit, the computational circuitry co-located with integrated memory circuit can be configured for performing supplemental functions at least partially during time periods that are not accessing intervals.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title MEMORY CIRCUITRY INCLUDING COMPUTATIONAL CIRCUITRY FOR PERFORMING SUPPLEMENTAL FUNCTIONS
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-26T14%3A41%3A25IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HYDE%20RODERICK%20A&rft.date=2014-07-24&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2014208041A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true