MANAGEMENT OF CACHE SIZE

MANAGEMENT OF CACHE SIZE

In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened pr...

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Hauptverfasser: KLASS RICHARD E, O'CONNOR JAMES M, MCLELLAN EDWARD J, KELTCHER PAUL, KALAMATIANOS JOHN, MANNE SRILATHA
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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creator KLASS RICHARD E
O'CONNOR JAMES M
MCLELLAN EDWARD J
KELTCHER PAUL
KALAMATIANOS JOHN
MANNE SRILATHA
description In response to a processor core exiting a low-power state, a cache is set to a minimum size so that fewer than all of the cache's entries are available to store data, thus reducing the cache's power consumption. Over time, the size of the cache can be increased to account for heightened processor activity, thus ensuring that processing efficiency is not significantly impacted by a reduced cache size. In some embodiments, the cache size is increased based on a measured processor performance metric, such as an eviction rate of the cache. In some embodiments, the cache size is increased at regular intervals until a maximum size is reached.
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title MANAGEMENT OF CACHE SIZE
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