SUSPEND SDRAM REFRESH CYCLES DURING NORMAL DDR OPERATION

SUSPEND SDRAM REFRESH CYCLES DURING NORMAL DDR OPERATION

An apparatus comprising a test circuit and a protocol circuit. The test circuit may be configured to generate a plurality of control signals in response to one or more read data signals. The protocol circuit may be configured to generate a plurality of interface signals in response to the plurality...

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: SINHA SHRUTI, ELLIS JACKSON L
Format: Patent
Sprache:eng
Schlagworte:
INFORMATION STORAGE
PHYSICS
STATIC STORES
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Beschreibung
Zusammenfassung:An apparatus comprising a test circuit and a protocol circuit. The test circuit may be configured to generate a plurality of control signals in response to one or more read data signals. The protocol circuit may be configured to generate a plurality of interface signals in response to the plurality of control signals. The protocol engine suspends a refresh operation during a normal operation of the apparatus.