REDUCTION OF METAL FILL INSERTION TIME IN INTEGRATED CIRCUIT DESIGN PROCESS

Techniques for use in integrated circuit design systems for reducing metal fill insertion time in the integrated circuit design process. In one example, a method includes the following steps. Metal fill data associated with a given layout from a placement and routing database of an integrated circui...

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Bibliographische Detailangaben

Hauptverfasser:	DAVIDOVIC GORAN, INDERST JUERGEN, KLEEBERGER RUPERT, PUGLIESE FULVIO
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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