SECONDARY BIT LINE EQUALIZER

Systems, methods, and other embodiments associated with bit line equalization are described. Systems and methods described herein provide secondary bit line equalization for embedded memory systems to reduce equalization time and improve memory performance. The reduction in equalization time is acco...

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Bibliographische Detailangaben

Hauptverfasser:	CHO HOYEOL, ORGINOS IOANNIS
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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