UNAUTHORIZED ACCESS AND/OR INSTRUCTION PREVENTION, DETECTION, AND/OR REMEDIATION, AT LEAST IN PART, BY STORAGE PROCESSOR
An embodiment may include a storage processor that may be comprised, at least in part, in a host. The host may include at least one host central processing unit (CPU) to execute at least one host operating system (OS). The storage processor may execute at least one operation in isolation from interf...
Gespeichert in:
| Hauptverfasser: | , , , , |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | SAXENA PARITOSH THADIKARAN PAUL J NEMIROFF DANIEL GAFKEN ANDREW H TRIANTAFILLOU NICHOLAS D |
| description | An embodiment may include a storage processor that may be comprised, at least in part, in a host. The host may include at least one host central processing unit (CPU) to execute at least one host operating system (OS). The storage processor may execute at least one operation in isolation from interference from and control by the at least one host CPU and the at least one host OS. The at least one operation may facilitate, at least in part: (1) prevention, at least in part, of unauthorized access to storage, (2) prevention, at least in part, of execution by the at least one host CPU of at least one unauthorized instruction, (3) detection, at least in part, of the at least one unauthorized instruction, and/or (4) remediation, at least in part, of at least one condition associated, at least in part, with the at least unauthorized instruction. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2014109170A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2014109170A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2014109170A13</originalsourceid><addsrcrecordid>eNqNjbEKwkAQRNNYiPoPC7YRcyqI5Xq36oHehb2NoE0IclaigVj4-SaYD7CaYXgzM0w-hcNCDp7tlQyg1hQCoDNzz2BdEC60WO8gZzqT62wKhoT0z_Yk04mMxT4TOBIGafuQI0sK2wsE8Yx7and8d-F5nAzu1aOJk15HyXRHog-zWL_K2NTVLT7juyzCIlMrlW3UOkO1_I_6AozzOtc</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>UNAUTHORIZED ACCESS AND/OR INSTRUCTION PREVENTION, DETECTION, AND/OR REMEDIATION, AT LEAST IN PART, BY STORAGE PROCESSOR</title><source>esp@cenet</source><creator>SAXENA PARITOSH ; THADIKARAN PAUL J ; NEMIROFF DANIEL ; GAFKEN ANDREW H ; TRIANTAFILLOU NICHOLAS D</creator><creatorcontrib>SAXENA PARITOSH ; THADIKARAN PAUL J ; NEMIROFF DANIEL ; GAFKEN ANDREW H ; TRIANTAFILLOU NICHOLAS D</creatorcontrib><description>An embodiment may include a storage processor that may be comprised, at least in part, in a host. The host may include at least one host central processing unit (CPU) to execute at least one host operating system (OS). The storage processor may execute at least one operation in isolation from interference from and control by the at least one host CPU and the at least one host OS. The at least one operation may facilitate, at least in part: (1) prevention, at least in part, of unauthorized access to storage, (2) prevention, at least in part, of execution by the at least one host CPU of at least one unauthorized instruction, (3) detection, at least in part, of the at least one unauthorized instruction, and/or (4) remediation, at least in part, of at least one condition associated, at least in part, with the at least unauthorized instruction.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140417&DB=EPODOC&CC=US&NR=2014109170A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20140417&DB=EPODOC&CC=US&NR=2014109170A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>SAXENA PARITOSH</creatorcontrib><creatorcontrib>THADIKARAN PAUL J</creatorcontrib><creatorcontrib>NEMIROFF DANIEL</creatorcontrib><creatorcontrib>GAFKEN ANDREW H</creatorcontrib><creatorcontrib>TRIANTAFILLOU NICHOLAS D</creatorcontrib><title>UNAUTHORIZED ACCESS AND/OR INSTRUCTION PREVENTION, DETECTION, AND/OR REMEDIATION, AT LEAST IN PART, BY STORAGE PROCESSOR</title><description>An embodiment may include a storage processor that may be comprised, at least in part, in a host. The host may include at least one host central processing unit (CPU) to execute at least one host operating system (OS). The storage processor may execute at least one operation in isolation from interference from and control by the at least one host CPU and the at least one host OS. The at least one operation may facilitate, at least in part: (1) prevention, at least in part, of unauthorized access to storage, (2) prevention, at least in part, of execution by the at least one host CPU of at least one unauthorized instruction, (3) detection, at least in part, of the at least one unauthorized instruction, and/or (4) remediation, at least in part, of at least one condition associated, at least in part, with the at least unauthorized instruction.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2014</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjbEKwkAQRNNYiPoPC7YRcyqI5Xq36oHehb2NoE0IclaigVj4-SaYD7CaYXgzM0w-hcNCDp7tlQyg1hQCoDNzz2BdEC60WO8gZzqT62wKhoT0z_Yk04mMxT4TOBIGafuQI0sK2wsE8Yx7and8d-F5nAzu1aOJk15HyXRHog-zWL_K2NTVLT7juyzCIlMrlW3UOkO1_I_6AozzOtc</recordid><startdate>20140417</startdate><enddate>20140417</enddate><creator>SAXENA PARITOSH</creator><creator>THADIKARAN PAUL J</creator><creator>NEMIROFF DANIEL</creator><creator>GAFKEN ANDREW H</creator><creator>TRIANTAFILLOU NICHOLAS D</creator><scope>EVB</scope></search><sort><creationdate>20140417</creationdate><title>UNAUTHORIZED ACCESS AND/OR INSTRUCTION PREVENTION, DETECTION, AND/OR REMEDIATION, AT LEAST IN PART, BY STORAGE PROCESSOR</title><author>SAXENA PARITOSH ; THADIKARAN PAUL J ; NEMIROFF DANIEL ; GAFKEN ANDREW H ; TRIANTAFILLOU NICHOLAS D</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2014109170A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2014</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>SAXENA PARITOSH</creatorcontrib><creatorcontrib>THADIKARAN PAUL J</creatorcontrib><creatorcontrib>NEMIROFF DANIEL</creatorcontrib><creatorcontrib>GAFKEN ANDREW H</creatorcontrib><creatorcontrib>TRIANTAFILLOU NICHOLAS D</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>SAXENA PARITOSH</au><au>THADIKARAN PAUL J</au><au>NEMIROFF DANIEL</au><au>GAFKEN ANDREW H</au><au>TRIANTAFILLOU NICHOLAS D</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>UNAUTHORIZED ACCESS AND/OR INSTRUCTION PREVENTION, DETECTION, AND/OR REMEDIATION, AT LEAST IN PART, BY STORAGE PROCESSOR</title><date>2014-04-17</date><risdate>2014</risdate><abstract>An embodiment may include a storage processor that may be comprised, at least in part, in a host. The host may include at least one host central processing unit (CPU) to execute at least one host operating system (OS). The storage processor may execute at least one operation in isolation from interference from and control by the at least one host CPU and the at least one host OS. The at least one operation may facilitate, at least in part: (1) prevention, at least in part, of unauthorized access to storage, (2) prevention, at least in part, of execution by the at least one host CPU of at least one unauthorized instruction, (3) detection, at least in part, of the at least one unauthorized instruction, and/or (4) remediation, at least in part, of at least one condition associated, at least in part, with the at least unauthorized instruction.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US2014109170A1 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | UNAUTHORIZED ACCESS AND/OR INSTRUCTION PREVENTION, DETECTION, AND/OR REMEDIATION, AT LEAST IN PART, BY STORAGE PROCESSOR |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-07T09%3A04%3A56IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=SAXENA%20PARITOSH&rft.date=2014-04-17&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2014109170A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |