METHOD AND APPARATUS FOR RECORDING AND PROFILING TRANSACTION FAILURE SOURCE ADDRESSES IN HARDWARE TRANSACTIONAL MEMORIES

A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retriev...

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Hauptverfasser:	EISEN SUSAN E, HALL CHARLES B, BLAINEY ROBERT J, MAY CATHY, CAIN HAROLD W, FREY BRADLY G, LE HUNG Q
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	EISEN SUSAN E HALL CHARLES B BLAINEY ROBERT J MAY CATHY CAIN HAROLD W FREY BRADLY G LE HUNG Q
description	A processor core includes a transactional memory, a transaction failure instruction address register (TFIAR), and a transaction failure data address register (TFDAR). The transactional memory stores information of a plurality of transactions executed by the processor core. The processor core retrieves instruction and data address associated with the aborted transaction from TFIAR and TFDAR respectively and stores them into a profiling table. The processor core then generates profiling information based on instruction and data addresses associated with the aborted transaction.
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title	METHOD AND APPARATUS FOR RECORDING AND PROFILING TRANSACTION FAILURE SOURCE ADDRESSES IN HARDWARE TRANSACTIONAL MEMORIES
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