SEMICONDUCTOR INTEGRATED CIRCUIT AND PATTERN LAYOUTING METHOD FOR THE SAME

SEMICONDUCTOR INTEGRATED CIRCUIT AND PATTERN LAYOUTING METHOD FOR THE SAME

A semiconductor integrated circuit and a pattern lay-outing method for the same are disclosed, which can suppress bending or partial drop-out of a dummy pattern even when a mechanical stress acts on the dummy pattern in CMP. The semiconductor integrated circuit includes predetermined functional area...

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1. Verfasser: KAMON KAZUYA
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
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creator KAMON KAZUYA
description A semiconductor integrated circuit and a pattern lay-outing method for the same are disclosed, which can suppress bending or partial drop-out of a dummy pattern even when a mechanical stress acts on the dummy pattern in CMP. The semiconductor integrated circuit includes predetermined functional areas and a dummy pattern formed in a space area. The space area is positioned between predetermined functional areas. The dummy pattern includes a first metal portion formed in the shape of a frame and defining an outer edge of the dummy pattern, a second metal portion positioned on an inner periphery side of the first metal portion and formed so as to be continuous with the first metal portion, and a plurality of non-forming areas positioned in an area where the second metal portion is not formed on the inner periphery side of the first metal portion.
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The dummy pattern includes a first metal portion formed in the shape of a frame and defining an outer edge of the dummy pattern, a second metal portion positioned on an inner periphery side of the first metal portion and formed so as to be continuous with the first metal portion, and a plurality of non-forming areas positioned in an area where the second metal portion is not formed on the inner periphery side of the first metal portion.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; PHYSICS ; SEMICONDUCTOR DEVICES</subject><creationdate>2014</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20140206&amp;DB=EPODOC&amp;CC=US&amp;NR=2014035108A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20140206&amp;DB=EPODOC&amp;CC=US&amp;NR=2014035108A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KAMON KAZUYA</creatorcontrib><title>SEMICONDUCTOR INTEGRATED CIRCUIT AND PATTERN LAYOUTING METHOD FOR THE SAME</title><description>A semiconductor integrated circuit and a pattern lay-outing method for the same are disclosed, which can suppress bending or partial drop-out of a dummy pattern even when a mechanical stress acts on the dummy pattern in CMP. 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subjects BASIC ELECTRIC ELEMENTS
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
PHYSICS
SEMICONDUCTOR DEVICES
title SEMICONDUCTOR INTEGRATED CIRCUIT AND PATTERN LAYOUTING METHOD FOR THE SAME
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