HYBRID TRANSISTOR

A hybrid transistor (58) has a substrate (42) with a first (e.g., P type) well region (46) and a second (e.g., N type) well region (44) with an NP or PN junction (43) therebetween. A MOS portion (70-3) of the hybrid transistor (58) has an (e.g., N type) source region (48) in the first well region (46) and a gate conductor (52) overlying and insulated from the well regions (46, 44) that extends laterally at least to the junction (43). A drain or anode (D/A) portion (71-3) in the second well region (44) collects current (69) from the source region (48), and includes a bipolar transistor (78) having an (e.g., N+) emitter region (64), a (e.g., P type) base region (59) and a (e.g., N type) collector region (62) laterally separated from the junction (43). Different LDMOS-like or IGBT-like properties are obtained depending on whether the current (69) is extracted from the hybrid transistor (58) via the bipolar transistor (78) base (59) or emitter (64) or both. The bipolar transistor (78) is desirably a vertical hetero junction transistor.