PROCESSES FOR FORMING INTEGRATED CIRCUITS WITH POST-PATTERNING TREAMENT

Processes for forming an integrated circuit are provided. In an embodiment, a process for forming an integrated circuit includes forming a low-k dielectric layer overlying a base substrate. An etch mask is patterned over the low-k dielectric layer. A recess is etched into the low-k dielectric layer through the etch mask to expose a recess surface within the recess. The low-k dielectric layer and the base substrate are annealed after etching. Annealing is conducted in an annealing environment, such as in an annealing furnace that provides the annealing environment. The recess surface is exposed to the annealing environment. An electrically-conductive material is deposited in the recess after annealing to form an embedded electrical interconnect.