Design Alteration for Wafer Inspection
Methods and systems for binning defects on a wafer are provided. One method includes identifying areas in a design for a layer of a device being fabricated on a wafer that are not critical to yield of fabrication of the device and generating an altered design for the layer by eliminating features in...
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| creator | PARK ALLEN CHANG ELLIS |
| description | Methods and systems for binning defects on a wafer are provided. One method includes identifying areas in a design for a layer of a device being fabricated on a wafer that are not critical to yield of fabrication of the device and generating an altered design for the layer by eliminating features in the identified areas from the design for the layer. The method also includes binning defects detected on the layer into groups using the altered design such that features in the altered design proximate positions of the defects in each of the groups are at least similar. |
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The method also includes binning defects detected on the layer into groups using the altered design such that features in the altered design proximate positions of the defects in each of the groups are at least similar.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFBzSS3OTM9TcMwpSS1KLMnMz1NIyy9SCE9MSy1S8MwrLkhNBgnyMLCmJeYUp_JCaW4GZTfXEGcP3dSC_PjU4oLE5NS81JL40GAjA0NjY0MLEwtTR0Nj4lQBAPP5KEw</recordid><startdate>20131128</startdate><enddate>20131128</enddate><creator>PARK ALLEN</creator><creator>CHANG ELLIS</creator><scope>EVB</scope></search><sort><creationdate>20131128</creationdate><title>Design Alteration for Wafer Inspection</title><author>PARK ALLEN ; CHANG ELLIS</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2013318485A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>PARK ALLEN</creatorcontrib><creatorcontrib>CHANG ELLIS</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>PARK ALLEN</au><au>CHANG ELLIS</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Design Alteration for Wafer Inspection</title><date>2013-11-28</date><risdate>2013</risdate><abstract>Methods and systems for binning defects on a wafer are provided. One method includes identifying areas in a design for a layer of a device being fabricated on a wafer that are not critical to yield of fabrication of the device and generating an altered design for the layer by eliminating features in the identified areas from the design for the layer. The method also includes binning defects detected on the layer into groups using the altered design such that features in the altered design proximate positions of the defects in each of the groups are at least similar.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Design Alteration for Wafer Inspection |
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