BUILT-IN SELF-TEST CIRCUIT APPLIED TO HIGH SPEED I/O PORT
A built-in self-test circuit (BIST) applied to a high speed I/O port is provided. The BIST circuit includes a detecting unit, a flag unit and a selecting unit. The detecting unit has a first input terminal for receiving a serial output signal, a second input terminal for receiving a serial enable si...
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creator | CHEN YU-LIN CHEN CHUNGING LIU HSIAN-FENG |
description | A built-in self-test circuit (BIST) applied to a high speed I/O port is provided. The BIST circuit includes a detecting unit, a flag unit and a selecting unit. The detecting unit has a first input terminal for receiving a serial output signal, a second input terminal for receiving a serial enable signal, and an output terminal for generating a detection signal. The flag unit receives the detection signal and generates a flag signal. The selecting unit receives the serial output signal, the serial enable signal and the flag signal. When a reset signal is at a first level, the selecting unit transmits the serial output signal and the serial enable signal to the I/O port. When the reset signal is at a second level, the serial output signal and the serial enable signal possesses a predetermined relationship. |
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The BIST circuit includes a detecting unit, a flag unit and a selecting unit. The detecting unit has a first input terminal for receiving a serial output signal, a second input terminal for receiving a serial enable signal, and an output terminal for generating a detection signal. The flag unit receives the detection signal and generates a flag signal. The selecting unit receives the serial output signal, the serial enable signal and the flag signal. When a reset signal is at a first level, the selecting unit transmits the serial output signal and the serial enable signal to the I/O port. When the reset signal is at a second level, the serial output signal and the serial enable signal possesses a predetermined relationship.</description><language>eng</language><subject>INFORMATION STORAGE ; PHYSICS ; STATIC STORES</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130801&DB=EPODOC&CC=US&NR=2013194876A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25543,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130801&DB=EPODOC&CC=US&NR=2013194876A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHEN YU-LIN</creatorcontrib><creatorcontrib>CHEN CHUNGING</creatorcontrib><creatorcontrib>LIU HSIAN-FENG</creatorcontrib><title>BUILT-IN SELF-TEST CIRCUIT APPLIED TO HIGH SPEED I/O PORT</title><description>A built-in self-test circuit (BIST) applied to a high speed I/O port is provided. The BIST circuit includes a detecting unit, a flag unit and a selecting unit. The detecting unit has a first input terminal for receiving a serial output signal, a second input terminal for receiving a serial enable signal, and an output terminal for generating a detection signal. The flag unit receives the detection signal and generates a flag signal. The selecting unit receives the serial output signal, the serial enable signal and the flag signal. When a reset signal is at a first level, the selecting unit transmits the serial output signal and the serial enable signal to the I/O port. When the reset signal is at a second level, the serial output signal and the serial enable signal possesses a predetermined relationship.</description><subject>INFORMATION STORAGE</subject><subject>PHYSICS</subject><subject>STATIC STORES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZLB0CvX0CdH19FMIdvVx0w1xDQ5RcPYMcg71DFFwDAjw8XR1UQjxV_DwdPdQCA5wBfI89f0VAvyDQngYWNMSc4pTeaE0N4Oym2uIs4duakF-fGpxQWJyal5qSXxosJGBobGhpYmFuZmjoTFxqgACTSlT</recordid><startdate>20130801</startdate><enddate>20130801</enddate><creator>CHEN YU-LIN</creator><creator>CHEN CHUNGING</creator><creator>LIU HSIAN-FENG</creator><scope>EVB</scope></search><sort><creationdate>20130801</creationdate><title>BUILT-IN SELF-TEST CIRCUIT APPLIED TO HIGH SPEED I/O PORT</title><author>CHEN YU-LIN ; CHEN CHUNGING ; LIU HSIAN-FENG</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2013194876A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>INFORMATION STORAGE</topic><topic>PHYSICS</topic><topic>STATIC STORES</topic><toplevel>online_resources</toplevel><creatorcontrib>CHEN YU-LIN</creatorcontrib><creatorcontrib>CHEN CHUNGING</creatorcontrib><creatorcontrib>LIU HSIAN-FENG</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHEN YU-LIN</au><au>CHEN CHUNGING</au><au>LIU HSIAN-FENG</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>BUILT-IN SELF-TEST CIRCUIT APPLIED TO HIGH SPEED I/O PORT</title><date>2013-08-01</date><risdate>2013</risdate><abstract>A built-in self-test circuit (BIST) applied to a high speed I/O port is provided. The BIST circuit includes a detecting unit, a flag unit and a selecting unit. The detecting unit has a first input terminal for receiving a serial output signal, a second input terminal for receiving a serial enable signal, and an output terminal for generating a detection signal. The flag unit receives the detection signal and generates a flag signal. The selecting unit receives the serial output signal, the serial enable signal and the flag signal. When a reset signal is at a first level, the selecting unit transmits the serial output signal and the serial enable signal to the I/O port. When the reset signal is at a second level, the serial output signal and the serial enable signal possesses a predetermined relationship.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | INFORMATION STORAGE PHYSICS STATIC STORES |
title | BUILT-IN SELF-TEST CIRCUIT APPLIED TO HIGH SPEED I/O PORT |
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