3D CHIP STACK HAVING ENCAPSULATED CHIP-IN-CHIP

3D CHIP STACK HAVING ENCAPSULATED CHIP-IN-CHIP

A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip...

Ausführliche Beschreibung

Gespeichert in:
Bibliographische Detailangaben
Hauptverfasser: HSU LOUIS LUN, CHENG KANGGUO, FAROOQ MUKTA G
Format: Patent
Sprache:eng
Schlagworte:
BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
Online-Zugang:Volltext bestellen
Tags: Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
container_end_page
container_issue
container_start_page
container_title
container_volume
creator HSU LOUIS LUN
CHENG KANGGUO
FAROOQ MUKTA G
description A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip is formed having second electrical devices. The second chip is then encapsulated within the recess of the first chip. Interconnects are then formed through the first chip into electrical communication with at least one of the second devices on the second chip. A three-dimensional (3D) chip is also provided in which a second chip is embedded within a first chip.
format Patent
fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2013193574A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2013193574A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2013193574A13</originalsourceid><addsrcrecordid>eNrjZNAzdlFw9vAMUAgOcXT2VvBwDPP0c1dw9XN2DAgO9XEMcYVI63r66YJoHgbWtMSc4lReKM3NoOzmGuLsoZtakB-fWlyQmJyal1oSHxpsZGBobGhpbGpu4mhoTJwqADr1Ji8</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>3D CHIP STACK HAVING ENCAPSULATED CHIP-IN-CHIP</title><source>esp@cenet</source><creator>HSU LOUIS LUN ; CHENG KANGGUO ; FAROOQ MUKTA G</creator><creatorcontrib>HSU LOUIS LUN ; CHENG KANGGUO ; FAROOQ MUKTA G</creatorcontrib><description>A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip is formed having second electrical devices. The second chip is then encapsulated within the recess of the first chip. Interconnects are then formed through the first chip into electrical communication with at least one of the second devices on the second chip. A three-dimensional (3D) chip is also provided in which a second chip is embedded within a first chip.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; SEMICONDUCTOR DEVICES</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20130801&amp;DB=EPODOC&amp;CC=US&amp;NR=2013193574A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20130801&amp;DB=EPODOC&amp;CC=US&amp;NR=2013193574A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>HSU LOUIS LUN</creatorcontrib><creatorcontrib>CHENG KANGGUO</creatorcontrib><creatorcontrib>FAROOQ MUKTA G</creatorcontrib><title>3D CHIP STACK HAVING ENCAPSULATED CHIP-IN-CHIP</title><description>A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip is formed having second electrical devices. The second chip is then encapsulated within the recess of the first chip. Interconnects are then formed through the first chip into electrical communication with at least one of the second devices on the second chip. A three-dimensional (3D) chip is also provided in which a second chip is embedded within a first chip.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNAzdlFw9vAMUAgOcXT2VvBwDPP0c1dw9XN2DAgO9XEMcYVI63r66YJoHgbWtMSc4lReKM3NoOzmGuLsoZtakB-fWlyQmJyal1oSHxpsZGBobGhpbGpu4mhoTJwqADr1Ji8</recordid><startdate>20130801</startdate><enddate>20130801</enddate><creator>HSU LOUIS LUN</creator><creator>CHENG KANGGUO</creator><creator>FAROOQ MUKTA G</creator><scope>EVB</scope></search><sort><creationdate>20130801</creationdate><title>3D CHIP STACK HAVING ENCAPSULATED CHIP-IN-CHIP</title><author>HSU LOUIS LUN ; CHENG KANGGUO ; FAROOQ MUKTA G</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2013193574A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>HSU LOUIS LUN</creatorcontrib><creatorcontrib>CHENG KANGGUO</creatorcontrib><creatorcontrib>FAROOQ MUKTA G</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>HSU LOUIS LUN</au><au>CHENG KANGGUO</au><au>FAROOQ MUKTA G</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>3D CHIP STACK HAVING ENCAPSULATED CHIP-IN-CHIP</title><date>2013-08-01</date><risdate>2013</risdate><abstract>A method of forming a three-dimensional (3D) chip is provided in which a second chip is present embedded within a first chip. In one embodiment, the method includes forming a first chip including first electrical devices and forming a recess extending from a surface of the first chip. A second chip is formed having second electrical devices. The second chip is then encapsulated within the recess of the first chip. Interconnects are then formed through the first chip into electrical communication with at least one of the second devices on the second chip. A three-dimensional (3D) chip is also provided in which a second chip is embedded within a first chip.</abstract><oa>free_for_read</oa></addata></record>
fulltext fulltext_linktorsrc
identifier
ispartof
issn
language eng
recordid cdi_epo_espacenet_US2013193574A1
source esp@cenet
subjects BASIC ELECTRIC ELEMENTS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
SEMICONDUCTOR DEVICES
title 3D CHIP STACK HAVING ENCAPSULATED CHIP-IN-CHIP
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-21T08%3A26%3A41IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=HSU%20LOUIS%20LUN&rft.date=2013-08-01&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2013193574A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true