Method And Apparatus For Accessing Physical Memory From A CPU Or Processing Element In A High Performance Manner

A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the vir...

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Hauptverfasser: MONDAL SANJOY K, SMITH LAWRENCE O, PATEL RAJESH B
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creator MONDAL SANJOY K
SMITH LAWRENCE O
PATEL RAJESH B
description A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the virtual memory addresses to physical addresses and provides the physical addresses to a common interface. Physical addressing logic decodes references to physical addresses and provides the physical addresses to a common interface based on a memory type stored by the physical addressing logic.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2013191603A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2013191603A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2013191603A13</originalsourceid><addsrcrecordid>eNqNirEKwjAUALs4iPoPD5yFxoLgGEpLHYoB7VxCfG0KzUt4iUP_3g66Oxw33G2z0GKy_gWSVkLQrNM7Qu0ZpDEY40QjKLvEyegZWnSeF6jZO5BQqg7uDIr9b6xmdEgJbrTmZhotKOTBs9NkEFpNhLzPNoOeIx6-3mXHunqWzQmD7zEGbZAw9d3jnItCXMUlL6Qo_rs-5PdBoQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Method And Apparatus For Accessing Physical Memory From A CPU Or Processing Element In A High Performance Manner</title><source>esp@cenet</source><creator>MONDAL SANJOY K ; SMITH LAWRENCE O ; PATEL RAJESH B</creator><creatorcontrib>MONDAL SANJOY K ; SMITH LAWRENCE O ; PATEL RAJESH B</creatorcontrib><description>A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the virtual memory addresses to physical addresses and provides the physical addresses to a common interface. Physical addressing logic decodes references to physical addresses and provides the physical addresses to a common interface based on a memory type stored by the physical addressing logic.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20130725&amp;DB=EPODOC&amp;CC=US&amp;NR=2013191603A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20130725&amp;DB=EPODOC&amp;CC=US&amp;NR=2013191603A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MONDAL SANJOY K</creatorcontrib><creatorcontrib>SMITH LAWRENCE O</creatorcontrib><creatorcontrib>PATEL RAJESH B</creatorcontrib><title>Method And Apparatus For Accessing Physical Memory From A CPU Or Processing Element In A High Performance Manner</title><description>A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the virtual memory addresses to physical addresses and provides the physical addresses to a common interface. Physical addressing logic decodes references to physical addresses and provides the physical addresses to a common interface based on a memory type stored by the physical addressing logic.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNirEKwjAUALs4iPoPD5yFxoLgGEpLHYoB7VxCfG0KzUt4iUP_3g66Oxw33G2z0GKy_gWSVkLQrNM7Qu0ZpDEY40QjKLvEyegZWnSeF6jZO5BQqg7uDIr9b6xmdEgJbrTmZhotKOTBs9NkEFpNhLzPNoOeIx6-3mXHunqWzQmD7zEGbZAw9d3jnItCXMUlL6Qo_rs-5PdBoQ</recordid><startdate>20130725</startdate><enddate>20130725</enddate><creator>MONDAL SANJOY K</creator><creator>SMITH LAWRENCE O</creator><creator>PATEL RAJESH B</creator><scope>EVB</scope></search><sort><creationdate>20130725</creationdate><title>Method And Apparatus For Accessing Physical Memory From A CPU Or Processing Element In A High Performance Manner</title><author>MONDAL SANJOY K ; SMITH LAWRENCE O ; PATEL RAJESH B</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2013191603A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>MONDAL SANJOY K</creatorcontrib><creatorcontrib>SMITH LAWRENCE O</creatorcontrib><creatorcontrib>PATEL RAJESH B</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MONDAL SANJOY K</au><au>SMITH LAWRENCE O</au><au>PATEL RAJESH B</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Method And Apparatus For Accessing Physical Memory From A CPU Or Processing Element In A High Performance Manner</title><date>2013-07-25</date><risdate>2013</risdate><abstract>A method and apparatus is described herein for accessing a physical memory location referenced by a physical address with a processor. The processor fetches/receives instructions with references to virtual memory addresses and/or references to physical addresses. Translation logic translates the virtual memory addresses to physical addresses and provides the physical addresses to a common interface. Physical addressing logic decodes references to physical addresses and provides the physical addresses to a common interface based on a memory type stored by the physical addressing logic.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title Method And Apparatus For Accessing Physical Memory From A CPU Or Processing Element In A High Performance Manner
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-01T14%3A23%3A35IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MONDAL%20SANJOY%20K&rft.date=2013-07-25&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2013191603A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true