MAPPING CIRCUIT TEST LOGIC BY ANALYZING REGISTER TRANSFER LEVEL CIRCUIT MODELS

Methods and systems for mapping and programming the debug logic of a circuit are provided. The system acquires a Register Transfer Level (RTL) representation of a circuit, wherein the circuit implements test logic that is externally programmable for providing one or more output signals corresponding to internal operational signals. The system analyzes the RTL representation to identify test multiplexers (MUXs) having registers for implementing the test logic, and correlates test register values for the test MUXs with outputs corresponding to the internal operational signals, based upon the RTL representation. The system further enables a user to select a desired internal operational signal for acquisition. Additionally, the system programs the test registers of the test MUXs of the circuit based on the correlated test register values to acquire the selected internal operational signal and to apply the acquired signal as one or more output signals.