Method and Apparatus for Simulating Gate Capacitance of a Tucked Transistor Device

A method for simulating a tucked transistor device having a diffusion region defined in a semiconductor layer, a gate electrode adjacent a first side of the diffusion region, a floating gate electrode adjacent a second side of the diffusion region, and an isolation structure disposed beneath at leas...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	RAMASUBRAMANIAN VENKAT, FARICELLI JOHN, GOO JUNG-SUK, THURUTHIYIL CIBY
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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