CRITICAL-PATH CIRCUIT FOR PERFORMANCE MONITORING

An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift register...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	CHLIPALA JAMES D, SEGAN SCOTT A, MUSCAVAGE RICHARD, MARTIN RICHARD P
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRONIC CIRCUITRY ELECTRICITY PULSE TECHNIQUE
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