CRITICAL-PATH CIRCUIT FOR PERFORMANCE MONITORING

An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift register...

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Hauptverfasser: CHLIPALA JAMES D, SEGAN SCOTT A, MUSCAVAGE RICHARD, MARTIN RICHARD P
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creator CHLIPALA JAMES D
SEGAN SCOTT A
MUSCAVAGE RICHARD
MARTIN RICHARD P
description An integrated circuit having a monitor circuit for monitoring timing in a critical path having a target timing margin is disclosed. The monitor circuit has two shift registers, one of which includes a delay element that applies a delay value to a received signal. The inputs to the two shift registers form a signal input node capable of receiving an input signal. The monitor circuit also has a logic gate having an output and at least two inputs, each input connected to a corresponding one of the outputs of the two shift registers. The output of the logic gate indicates whether the target timing margin is satisfied or not satisfied.
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subjects BASIC ELECTRONIC CIRCUITRY
ELECTRICITY
PULSE TECHNIQUE
title CRITICAL-PATH CIRCUIT FOR PERFORMANCE MONITORING
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