Performing An Atomic Operation Without Quiescing An Interconnect Structure
In one embodiment, the present invention includes a method for receiving a lock message for an address in a processor from a quiesce master of a system. This lock message indicates that a requester agent of the system is to enter a locking phase with respect to the address. Responsive to receipt of...
Gespeichert in:
| 1. Verfasser: | |
|---|---|
| Format: | Patent |
| Sprache: | eng |
| Schlagworte: | |
| Online-Zugang: | Volltext bestellen |
| Tags: |
Tag hinzufügen
Keine Tags, Fügen Sie den ersten Tag hinzu!
|
| container_end_page | |
|---|---|
| container_issue | |
| container_start_page | |
| container_title | |
| container_volume | |
| creator | CHEE PIK SHEN |
| description | In one embodiment, the present invention includes a method for receiving a lock message for an address in a processor from a quiesce master of a system. This lock message indicates that a requester agent of the system is to enter a locking phase with respect to the address. Responsive to receipt of this message, logic of the processor can write an entry in a tracking buffer of the processor for the address and thereafter allow a transaction to be sent from the processor via an interconnect if an address of the transaction does not match any address stored in the tracking buffer. Other embodiments are described and claimed. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2013054915A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2013054915A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2013054915A13</originalsourceid><addsrcrecordid>eNqNyrEKwjAQANAsDqL-w4Gz0Fg7dAyiqItKFccSjqsG7CVcLv_v0g9wesubm8uNZIgyBn6DY3Aax4BwTSReQ2R4Bf3EonAvgTJO68xKgpGZUKFTKahFaGlmg_9mWk0uzPp4eOxPG0qxp5w8EpP2z25b2bpqdq1tnK3_Wz_ocTX_</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Performing An Atomic Operation Without Quiescing An Interconnect Structure</title><source>esp@cenet</source><creator>CHEE PIK SHEN</creator><creatorcontrib>CHEE PIK SHEN</creatorcontrib><description>In one embodiment, the present invention includes a method for receiving a lock message for an address in a processor from a quiesce master of a system. This lock message indicates that a requester agent of the system is to enter a locking phase with respect to the address. Responsive to receipt of this message, logic of the processor can write an entry in a tracking buffer of the processor for the address and thereafter allow a transaction to be sent from the processor via an interconnect if an address of the transaction does not match any address stored in the tracking buffer. Other embodiments are described and claimed.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2013</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130228&DB=EPODOC&CC=US&NR=2013054915A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20130228&DB=EPODOC&CC=US&NR=2013054915A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>CHEE PIK SHEN</creatorcontrib><title>Performing An Atomic Operation Without Quiescing An Interconnect Structure</title><description>In one embodiment, the present invention includes a method for receiving a lock message for an address in a processor from a quiesce master of a system. This lock message indicates that a requester agent of the system is to enter a locking phase with respect to the address. Responsive to receipt of this message, logic of the processor can write an entry in a tracking buffer of the processor for the address and thereafter allow a transaction to be sent from the processor via an interconnect if an address of the transaction does not match any address stored in the tracking buffer. Other embodiments are described and claimed.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2013</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyrEKwjAQANAsDqL-w4Gz0Fg7dAyiqItKFccSjqsG7CVcLv_v0g9wesubm8uNZIgyBn6DY3Aax4BwTSReQ2R4Bf3EonAvgTJO68xKgpGZUKFTKahFaGlmg_9mWk0uzPp4eOxPG0qxp5w8EpP2z25b2bpqdq1tnK3_Wz_ocTX_</recordid><startdate>20130228</startdate><enddate>20130228</enddate><creator>CHEE PIK SHEN</creator><scope>EVB</scope></search><sort><creationdate>20130228</creationdate><title>Performing An Atomic Operation Without Quiescing An Interconnect Structure</title><author>CHEE PIK SHEN</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2013054915A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2013</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>CHEE PIK SHEN</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>CHEE PIK SHEN</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Performing An Atomic Operation Without Quiescing An Interconnect Structure</title><date>2013-02-28</date><risdate>2013</risdate><abstract>In one embodiment, the present invention includes a method for receiving a lock message for an address in a processor from a quiesce master of a system. This lock message indicates that a requester agent of the system is to enter a locking phase with respect to the address. Responsive to receipt of this message, logic of the processor can write an entry in a tracking buffer of the processor for the address and thereafter allow a transaction to be sent from the processor via an interconnect if an address of the transaction does not match any address stored in the tracking buffer. Other embodiments are described and claimed.</abstract><oa>free_for_read</oa></addata></record> |
| fulltext | fulltext_linktorsrc |
| identifier | |
| ispartof | |
| issn | |
| language | eng |
| recordid | cdi_epo_espacenet_US2013054915A1 |
| source | esp@cenet |
| subjects | CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS |
| title | Performing An Atomic Operation Without Quiescing An Interconnect Structure |
| url | https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-28T05%3A06%3A27IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=CHEE%20PIK%20SHEN&rft.date=2013-02-28&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2013054915A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true |