SYSTEM AND METHOD FOR REDUCING POWER CONSUMPTION IN A PHASED-LOCKED LOOP CIRCUIT

A phased-locked loop (PLL) circuit which comprises a phase-frequency detector (PFD) configured to receive a reference signal, a voltage-controlled oscillator (VCO) configured to produce a VCO signal, and a divider configured to divide the VCO signal thereby producing a feedback signal based on the f...

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Hauptverfasser:	NAGARAJ KRISHNASAWAMY, KUMAR AJAY
Format:	Patent
Sprache:	eng
Schlagworte:	AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATIONOF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES BASIC ELECTRONIC CIRCUITRY DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TOANOTHER ELECTRICITY
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