FLIP-FLOP CIRCUIT, SCAN TEST CIRCUIT, AND METHOD OF CONTROLLING SCAN TEST CIRCUIT

Provided is a flip-flop circuit which a small-sized test circuit with hold free and can perform test in an actual operating frequency. A Pos-type F/F includes a master latch (Low level latch) that selectively receives data or scan test data in synchronization with a rising edge of a clock signal, and a slave latch (High level latch) that receives the data from the master latch. In a scan shift operation, the master latch captures scan data signal input SIN in a Low period of a scan shift clock signal SCLK1 and outputs the data to the slave latch. The slave latch captures the output of the master latch in a High period of a scan shift clock signal SCLK2 having a different edge position from the SCLK1 and outputs the data to Q.