CONNECTION USING CONDUCTIVE VIAS

In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuit...

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Hauptverfasser: MADSEN ULRIK RIIS, MORRIS THOMAS SCOTT, LEAHY DONALD JOSEPH
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creator MADSEN ULRIK RIIS
MORRIS THOMAS SCOTT
LEAHY DONALD JOSEPH
description In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2012217624A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2012217624A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2012217624A13</originalsourceid><addsrcrecordid>eNrjZFBw9vfzc3UO8fT3UwgN9vRzBwm4hAIFwlwVwjwdg3kYWNMSc4pTeaE0N4Oym2uIs4duakF-fGpxQWJyal5qSXxosJGBoZGRobmZkYmjoTFxqgCLhCLu</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CONNECTION USING CONDUCTIVE VIAS</title><source>esp@cenet</source><creator>MADSEN ULRIK RIIS ; MORRIS THOMAS SCOTT ; LEAHY DONALD JOSEPH</creator><creatorcontrib>MADSEN ULRIK RIIS ; MORRIS THOMAS SCOTT ; LEAHY DONALD JOSEPH</creatorcontrib><description>In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC ; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES ; TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ; TECHNICAL SUBJECTS COVERED BY FORMER USPC ; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120830&amp;DB=EPODOC&amp;CC=US&amp;NR=2012217624A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120830&amp;DB=EPODOC&amp;CC=US&amp;NR=2012217624A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>MADSEN ULRIK RIIS</creatorcontrib><creatorcontrib>MORRIS THOMAS SCOTT</creatorcontrib><creatorcontrib>LEAHY DONALD JOSEPH</creatorcontrib><title>CONNECTION USING CONDUCTIVE VIAS</title><description>In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</subject><subject>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZFBw9vfzc3UO8fT3UwgN9vRzBwm4hAIFwlwVwjwdg3kYWNMSc4pTeaE0N4Oym2uIs4duakF-fGpxQWJyal5qSXxosJGBoZGRobmZkYmjoTFxqgCLhCLu</recordid><startdate>20120830</startdate><enddate>20120830</enddate><creator>MADSEN ULRIK RIIS</creator><creator>MORRIS THOMAS SCOTT</creator><creator>LEAHY DONALD JOSEPH</creator><scope>EVB</scope></search><sort><creationdate>20120830</creationdate><title>CONNECTION USING CONDUCTIVE VIAS</title><author>MADSEN ULRIK RIIS ; MORRIS THOMAS SCOTT ; LEAHY DONALD JOSEPH</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2012217624A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</topic><topic>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</topic><toplevel>online_resources</toplevel><creatorcontrib>MADSEN ULRIK RIIS</creatorcontrib><creatorcontrib>MORRIS THOMAS SCOTT</creatorcontrib><creatorcontrib>LEAHY DONALD JOSEPH</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>MADSEN ULRIK RIIS</au><au>MORRIS THOMAS SCOTT</au><au>LEAHY DONALD JOSEPH</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CONNECTION USING CONDUCTIVE VIAS</title><date>2012-08-30</date><risdate>2012</risdate><abstract>In one embodiment, a meta-module having circuitry for two or more modules is formed on a substrate, which is preferably a laminated substrate. The circuitry for the different modules is initially formed on the single meta-module. Each module will have one or more component areas in which the circuitry is formed. A metallic structure is formed on or in the substrate for each component area to be shielded. A single body, such as an overmold body, is then formed over all of the modules on the meta-module. At least a conductive vertical interconnect access structure (vias) associated with each component area to be shielded is then exposed through the body by a cutting, drilling, or similar operation. Next, an electromagnetic shield material is applied to the exterior surface of the body of each of the component areas to be shielded and in contact with the exposed conductive vias.</abstract><oa>free_for_read</oa></addata></record>
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subjects BASIC ELECTRIC ELEMENTS
CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
SEMICONDUCTOR DEVICES
TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
TECHNICAL SUBJECTS COVERED BY FORMER USPC
TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
title CONNECTION USING CONDUCTIVE VIAS
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-01-30T21%3A57%3A55IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=MADSEN%20ULRIK%20RIIS&rft.date=2012-08-30&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2012217624A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true