Robust Hamming Code Implementation for Soft Error Detection, Correction, and Reporting in a Multi-Level Cache System Using Dual Banking Memory Scheme
The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate...
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| creator | TRAN JONATHAN (SON) HUNG GURRAM KRISHNA CHAITHANYA ZBICIAK JOSEPH RAYMOND MICHAEL CHACHAD ABHIJEET ASHOK |
| description | The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks. |
| format | Patent |
| fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2012192027A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2012192027A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2012192027A13</originalsourceid><addsrcrecordid>eNqNjM0KglAQhd20iOodBtomqC2iZalhkBvNtUw6lnR_5N4x8EF63xRq3-p8h_Nx5s4707feMiQoZavuEOqa4Cw7QZIUI7daQaMN5LphiI0ZMSKmaho2o23Mj1HVkFGnDU8_rQKEtBfcuhd6kYAQqwdBPlgmCYWdnKhHAUdUz6mkJLUZIB8tSUtn1qCwtPrmwlmf4muYuON_SbbDihRxWeSB5wf-PvCC3cHf_md9AGi3UCM</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>Robust Hamming Code Implementation for Soft Error Detection, Correction, and Reporting in a Multi-Level Cache System Using Dual Banking Memory Scheme</title><source>esp@cenet</source><creator>TRAN JONATHAN (SON) HUNG ; GURRAM KRISHNA CHAITHANYA ; ZBICIAK JOSEPH RAYMOND MICHAEL ; CHACHAD ABHIJEET ASHOK</creator><creatorcontrib>TRAN JONATHAN (SON) HUNG ; GURRAM KRISHNA CHAITHANYA ; ZBICIAK JOSEPH RAYMOND MICHAEL ; CHACHAD ABHIJEET ASHOK</creatorcontrib><description>The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.</description><language>eng</language><subject>BASIC ELECTRONIC CIRCUITRY ; CALCULATING ; CODE CONVERSION IN GENERAL ; CODING ; COMPUTING ; COUNTING ; DECODING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRICITY ; PHYSICS</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20120726&DB=EPODOC&CC=US&NR=2012192027A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76290</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20120726&DB=EPODOC&CC=US&NR=2012192027A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>TRAN JONATHAN (SON) HUNG</creatorcontrib><creatorcontrib>GURRAM KRISHNA CHAITHANYA</creatorcontrib><creatorcontrib>ZBICIAK JOSEPH RAYMOND MICHAEL</creatorcontrib><creatorcontrib>CHACHAD ABHIJEET ASHOK</creatorcontrib><title>Robust Hamming Code Implementation for Soft Error Detection, Correction, and Reporting in a Multi-Level Cache System Using Dual Banking Memory Scheme</title><description>The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.</description><subject>BASIC ELECTRONIC CIRCUITRY</subject><subject>CALCULATING</subject><subject>CODE CONVERSION IN GENERAL</subject><subject>CODING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>DECODING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRICITY</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjM0KglAQhd20iOodBtomqC2iZalhkBvNtUw6lnR_5N4x8EF63xRq3-p8h_Nx5s4707feMiQoZavuEOqa4Cw7QZIUI7daQaMN5LphiI0ZMSKmaho2o23Mj1HVkFGnDU8_rQKEtBfcuhd6kYAQqwdBPlgmCYWdnKhHAUdUz6mkJLUZIB8tSUtn1qCwtPrmwlmf4muYuON_SbbDihRxWeSB5wf-PvCC3cHf_md9AGi3UCM</recordid><startdate>20120726</startdate><enddate>20120726</enddate><creator>TRAN JONATHAN (SON) HUNG</creator><creator>GURRAM KRISHNA CHAITHANYA</creator><creator>ZBICIAK JOSEPH RAYMOND MICHAEL</creator><creator>CHACHAD ABHIJEET ASHOK</creator><scope>EVB</scope></search><sort><creationdate>20120726</creationdate><title>Robust Hamming Code Implementation for Soft Error Detection, Correction, and Reporting in a Multi-Level Cache System Using Dual Banking Memory Scheme</title><author>TRAN JONATHAN (SON) HUNG ; GURRAM KRISHNA CHAITHANYA ; ZBICIAK JOSEPH RAYMOND MICHAEL ; CHACHAD ABHIJEET ASHOK</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2012192027A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><topic>BASIC ELECTRONIC CIRCUITRY</topic><topic>CALCULATING</topic><topic>CODE CONVERSION IN GENERAL</topic><topic>CODING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>DECODING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRICITY</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>TRAN JONATHAN (SON) HUNG</creatorcontrib><creatorcontrib>GURRAM KRISHNA CHAITHANYA</creatorcontrib><creatorcontrib>ZBICIAK JOSEPH RAYMOND MICHAEL</creatorcontrib><creatorcontrib>CHACHAD ABHIJEET ASHOK</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>TRAN JONATHAN (SON) HUNG</au><au>GURRAM KRISHNA CHAITHANYA</au><au>ZBICIAK JOSEPH RAYMOND MICHAEL</au><au>CHACHAD ABHIJEET ASHOK</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>Robust Hamming Code Implementation for Soft Error Detection, Correction, and Reporting in a Multi-Level Cache System Using Dual Banking Memory Scheme</title><date>2012-07-26</date><risdate>2012</risdate><abstract>The invention is a memory system having two memory banks which can store and recall with memory error detection and correction on data of two different sizes. For writing separate parity generators form parity bits for respective memory banks. For reading separate parity detector/generators operate on data of separate memory banks.</abstract><oa>free_for_read</oa></addata></record> |
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| subjects | BASIC ELECTRONIC CIRCUITRY CALCULATING CODE CONVERSION IN GENERAL CODING COMPUTING COUNTING DECODING ELECTRIC DIGITAL DATA PROCESSING ELECTRICITY PHYSICS |
| title | Robust Hamming Code Implementation for Soft Error Detection, Correction, and Reporting in a Multi-Level Cache System Using Dual Banking Memory Scheme |
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