CORELESS LAYER BUILDUP STRUCTURE WITH LGA

CORELESS LAYER BUILDUP STRUCTURE WITH LGA

A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (...

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Hauptverfasser: WILSON WILLIAM E, DAS RABINDRA N, EGITTO FRANK D, ANTESBERGER TIMOTHY, MARKOVICH VOYA R
Format: Patent
Sprache:eng
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CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
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creator WILSON WILLIAM E
DAS RABINDRA N
EGITTO FRANK D
ANTESBERGER TIMOTHY
MARKOVICH VOYA R
description A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2012160544A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2012160544A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2012160544A13</originalsourceid><addsrcrecordid>eNrjZNB09g9y9XENDlbwcYx0DVJwCvX0cQkNUAgOCQp1DgkNclUI9wzxUPBxd-RhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGhkaGZgamJiaOhsbEqQIA0PIlaQ</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>CORELESS LAYER BUILDUP STRUCTURE WITH LGA</title><source>esp@cenet</source><creator>WILSON WILLIAM E ; DAS RABINDRA N ; EGITTO FRANK D ; ANTESBERGER TIMOTHY ; MARKOVICH VOYA R</creator><creatorcontrib>WILSON WILLIAM E ; DAS RABINDRA N ; EGITTO FRANK D ; ANTESBERGER TIMOTHY ; MARKOVICH VOYA R</creatorcontrib><description>A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.</description><language>eng</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120628&amp;DB=EPODOC&amp;CC=US&amp;NR=2012160544A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20120628&amp;DB=EPODOC&amp;CC=US&amp;NR=2012160544A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>WILSON WILLIAM E</creatorcontrib><creatorcontrib>DAS RABINDRA N</creatorcontrib><creatorcontrib>EGITTO FRANK D</creatorcontrib><creatorcontrib>ANTESBERGER TIMOTHY</creatorcontrib><creatorcontrib>MARKOVICH VOYA R</creatorcontrib><title>CORELESS LAYER BUILDUP STRUCTURE WITH LGA</title><description>A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZNB09g9y9XENDlbwcYx0DVJwCvX0cQkNUAgOCQp1DgkNclUI9wzxUPBxd-RhYE1LzClO5YXS3AzKbq4hzh66qQX58anFBYnJqXmpJfGhwUYGhkaGZgamJiaOhsbEqQIA0PIlaQ</recordid><startdate>20120628</startdate><enddate>20120628</enddate><creator>WILSON WILLIAM E</creator><creator>DAS RABINDRA N</creator><creator>EGITTO FRANK D</creator><creator>ANTESBERGER TIMOTHY</creator><creator>MARKOVICH VOYA R</creator><scope>EVB</scope></search><sort><creationdate>20120628</creationdate><title>CORELESS LAYER BUILDUP STRUCTURE WITH LGA</title><author>WILSON WILLIAM E ; DAS RABINDRA N ; EGITTO FRANK D ; ANTESBERGER TIMOTHY ; MARKOVICH VOYA R</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2012160544A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><toplevel>online_resources</toplevel><creatorcontrib>WILSON WILLIAM E</creatorcontrib><creatorcontrib>DAS RABINDRA N</creatorcontrib><creatorcontrib>EGITTO FRANK D</creatorcontrib><creatorcontrib>ANTESBERGER TIMOTHY</creatorcontrib><creatorcontrib>MARKOVICH VOYA R</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>WILSON WILLIAM E</au><au>DAS RABINDRA N</au><au>EGITTO FRANK D</au><au>ANTESBERGER TIMOTHY</au><au>MARKOVICH VOYA R</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>CORELESS LAYER BUILDUP STRUCTURE WITH LGA</title><date>2012-06-28</date><risdate>2012</risdate><abstract>A substrate for use in a PCB or PWB board having a coreless buildup layer and at least one metal and at least one dielectric layer. The coreless buildup dielectric layers can consist of at least partially cured thermoset resin and thermoplastic resin. The substrate may also contain land grid array (LGA) packaging.</abstract><oa>free_for_read</oa></addata></record>
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subjects CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
PRINTED CIRCUITS
title CORELESS LAYER BUILDUP STRUCTURE WITH LGA
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2024-12-18T23%3A59%3A44IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=WILSON%20WILLIAM%20E&rft.date=2012-06-28&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2012160544A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true