REDUCING POWER CONSUMPTION IN MULTI-PRECISION FLOATING POINT MULTIPLIERS

REDUCING POWER CONSUMPTION IN MULTI-PRECISION FLOATING POINT MULTIPLIERS

Methods and apparatus relating to reducing power consumption in multi-precision floating point multipliers are described. In an embodiment, certain portions of a multiplier are disabled in response to two or more multiplication operations with the same data size and data type occurring back-to-back....

Ausführliche Beschreibung

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Bibliographische Detailangaben
Hauptverfasser: PONS THIERRY, BOSWELL BRENT R, AVIRAM TOM
Format: Patent
Sprache:eng
Schlagworte:
CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
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Beschreibung
Zusammenfassung:Methods and apparatus relating to reducing power consumption in multi-precision floating point multipliers are described. In an embodiment, certain portions of a multiplier are disabled in response to two or more multiplication operations with the same data size and data type occurring back-to-back. Other embodiments are also claimed and described.