PARTITIONING FOR HARDWARE-ACCELERATED FUNCTIONAL VERIFICATION

A circuit design is partitioned for hardware-accelerated functional verification using a directed hypergraph with edge weights that are a function of slack. Slack may be computed as the difference between the early and late ranks for the source of an edge. The weight may further be computed as the d...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	MOFFITT MICHAEL D, SUSTIK MATYAS A, VILLARRUBIA PAUL G
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!