PROCESSOR AND VECTOR LOAD INSTRUCTION EXECUTION METHOD

Provided is a processor including an instruction issue unit that issues a vector load instruction read from a main memory based on branch target prediction of a branch target in a branch instruction, a data acquisition unit that starts issue of a plurality of acquisition requests for acquiring a plu...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	FUKAGAWA MASAO
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
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