VERTICAL TRANSISTOR WITH HARDENING IMPLATATION

A method includes providing a semiconductor wafer having a plurality of pillar structures extending orthogonally from the semiconductor wafer. Each pillar structure forms a vertical pillar transistor having a top surface and a side surface orthogonal to the top surface. Then a hardening species is i...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	JUNG CHULMIN, MANOS PETER NICHOLAS, SETIADI DADI, KHOURY MAROUN GEORGES, KIM YOUNG PIL, LEE HYUNG-KYU
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY SEMICONDUCTOR DEVICES
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