SCAN OR JTAG CONTROLLABLE CAPTURE CLOCK GENERATION

A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The sc...

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Hauptverfasser:	KADIYALA ANIRUDH, GORTI ATCHYUTH K, KWAN BILL K, KUCHIPUDI VENKAT K
Format:	Patent
Sprache:	eng
Schlagworte:	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING
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creator	KADIYALA ANIRUDH GORTI ATCHYUTH K KWAN BILL K KUCHIPUDI VENKAT K
description	A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection.
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fullrecord	<record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2012062266A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2012062266A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2012062266A13</originalsourceid><addsrcrecordid>eNrjZDAKdnb0U_APUvAKcXRXcPb3Cwny9_FxdPJxVXB2DAgJDQLSPv7O3grurn6uQY4hnv5-PAysaYk5xam8UJqbQdnNNcTZQze1ID8-tbggMTk1L7UkPjTYyMDQyMDMyMjMzNHQmDhVAAJAJ5w</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>SCAN OR JTAG CONTROLLABLE CAPTURE CLOCK GENERATION</title><source>esp@cenet</source><creator>KADIYALA ANIRUDH ; GORTI ATCHYUTH K ; KWAN BILL K ; KUCHIPUDI VENKAT K</creator><creatorcontrib>KADIYALA ANIRUDH ; GORTI ATCHYUTH K ; KWAN BILL K ; KUCHIPUDI VENKAT K</creatorcontrib><description>A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MEASURING ; MEASURING ELECTRIC VARIABLES ; MEASURING MAGNETIC VARIABLES ; PHYSICS ; SEMICONDUCTOR DEVICES ; TESTING</subject><creationdate>2012</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20120315&DB=EPODOC&CC=US&NR=2012062266A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20120315&DB=EPODOC&CC=US&NR=2012062266A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>KADIYALA ANIRUDH</creatorcontrib><creatorcontrib>GORTI ATCHYUTH K</creatorcontrib><creatorcontrib>KWAN BILL K</creatorcontrib><creatorcontrib>KUCHIPUDI VENKAT K</creatorcontrib><title>SCAN OR JTAG CONTROLLABLE CAPTURE CLOCK GENERATION</title><description>A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MEASURING</subject><subject>MEASURING ELECTRIC VARIABLES</subject><subject>MEASURING MAGNETIC VARIABLES</subject><subject>PHYSICS</subject><subject>SEMICONDUCTOR DEVICES</subject><subject>TESTING</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2012</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZDAKdnb0U_APUvAKcXRXcPb3Cwny9_FxdPJxVXB2DAgJDQLSPv7O3grurn6uQY4hnv5-PAysaYk5xam8UJqbQdnNNcTZQze1ID8-tbggMTk1L7UkPjTYyMDQyMDMyMjMzNHQmDhVAAJAJ5w</recordid><startdate>20120315</startdate><enddate>20120315</enddate><creator>KADIYALA ANIRUDH</creator><creator>GORTI ATCHYUTH K</creator><creator>KWAN BILL K</creator><creator>KUCHIPUDI VENKAT K</creator><scope>EVB</scope></search><sort><creationdate>20120315</creationdate><title>SCAN OR JTAG CONTROLLABLE CAPTURE CLOCK GENERATION</title><author>KADIYALA ANIRUDH ; GORTI ATCHYUTH K ; KWAN BILL K ; KUCHIPUDI VENKAT K</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2012062266A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2012</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MEASURING</topic><topic>MEASURING ELECTRIC VARIABLES</topic><topic>MEASURING MAGNETIC VARIABLES</topic><topic>PHYSICS</topic><topic>SEMICONDUCTOR DEVICES</topic><topic>TESTING</topic><toplevel>online_resources</toplevel><creatorcontrib>KADIYALA ANIRUDH</creatorcontrib><creatorcontrib>GORTI ATCHYUTH K</creatorcontrib><creatorcontrib>KWAN BILL K</creatorcontrib><creatorcontrib>KUCHIPUDI VENKAT K</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>KADIYALA ANIRUDH</au><au>GORTI ATCHYUTH K</au><au>KWAN BILL K</au><au>KUCHIPUDI VENKAT K</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>SCAN OR JTAG CONTROLLABLE CAPTURE CLOCK GENERATION</title><date>2012-03-15</date><risdate>2012</risdate><abstract>A capture clock generation control mechanism is provided. The capture clock generation control mechanism controls the number of at-speed clocks generated and supplied to one or more scan chains during scan testing of a microcircuit based on control data stored in a JTAG or scan test register. The scan test register may be formed out of scan cells and comprise part of a scan chain. Automatic Test Pattern Generation (ATPG) tools may generate the data that is loaded into the scan test register to automatically configure the clock generation control mechanism. The clock control mechanism may include the ability to adjust the position of the at-speed clocks within a capture cycle, thereby facilitating transition fault detection.</abstract><oa>free_for_read</oa></addata></record>
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subjects	BASIC ELECTRIC ELEMENTS CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRICITY MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS SEMICONDUCTOR DEVICES TESTING
title	SCAN OR JTAG CONTROLLABLE CAPTURE CLOCK GENERATION
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