BUS ARBITRATION APPARATUS

An arbitration circuit 108 receives a read/write request from a master 101, such as a CPU, in which low latency is required, at a regular interval, such that the master 101 performs memory access with low latency. A remaining band which is not used by the master 101 is allocated to masters 102 and 1...

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Hauptverfasser:	MAEDA TAKASHI, HASHIMOTO KOUKICHI, MATSUSHITA MASATOSHI, SUMIDA MAMORU
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
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creator	MAEDA TAKASHI HASHIMOTO KOUKICHI MATSUSHITA MASATOSHI SUMIDA MAMORU
description	An arbitration circuit 108 receives a read/write request from a master 101, such as a CPU, in which low latency is required, at a regular interval, such that the master 101 performs memory access with low latency. A remaining band which is not used by the master 101 is allocated to masters 102 and 103, such as a DMA controller, in which a wideband is required, thereby ensuring a necessary band. When a read/write request is retained in a buffer 119 of a slave 118, the arbitration circuit 108 suppresses the acceptance of the read/write requests from the masters 102 and 103 having low priority. Therefore, it is possible to provide a bus arbitration apparatus capable of transmitting a request from a specific master to a slave with low latency, and to ensure a band necessary for another master.
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subjects	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
title	BUS ARBITRATION APPARATUS
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