G-ODLAT On-die Logic Analyzer Trigger with Parallel Vector Finite State Machine

An apparatus for debugging internal signals of integrated circuits is presented. In one embodiment, the apparatus comprises a number of vector registers associated with states of a state machine. A group of registers, associated with a state of the state machine, comprises a mask register an arm reg...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	SKABA DANIEL, ISRAELI MICHAEL, MANDELBLAT JULIUS, KURTS TSVIKA, SAMOELOV ITAI
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING MEASURING MEASURING ELECTRIC VARIABLES MEASURING MAGNETIC VARIABLES PHYSICS TESTING
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