WIRING BOARD, ELECTRONIC DEVICE PACKAGE, AND METHODS OF PRODUCTION OF THE SAME

A wiring board which uses both conductor patterns and reflection members provided at gaps therebetween to suppress unevenness in the reflection rate so as to raise the overall reflection rate and provide a reflection function on the surface of the wiring board at the side where an electronic device...

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Hauptverfasser: YOSHIDA HIDEKI, ISODA SATOSHI, URASAKI NAOYUKI, KOTANI HAYATO
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Sprache:eng
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creator YOSHIDA HIDEKI
ISODA SATOSHI
URASAKI NAOYUKI
KOTANI HAYATO
description A wiring board which uses both conductor patterns and reflection members provided at gaps therebetween to suppress unevenness in the reflection rate so as to raise the overall reflection rate and provide a reflection function on the surface of the wiring board at the side where an electronic device is mounted; facilitates shaping of the reflection members, controlling of the thickness of the reflection members, and controlling of the surface shape of the reflection members so as to stabilize the reflection rate; and secures close contact between the reflection members and sealing members so as to improve reliability. The wiring board comprises a plurality of wiring layers provided with conductor patterns disposed on base members, and base members which electrically insulate the plurality of wiring layers. At the outermost wiring layer among the plurality of wiring layers, reflection members are formed on the portions of the base member where there are no conductor patterns, the surface of these reflection members and the surface of the conductor patterns are made level and the surface of the conductor patterns are exposed from the reflection members.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2011297424A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2011297424A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2011297424A13</originalsourceid><addsrcrecordid>eNrjZPAL9wzy9HNXcPJ3DHLRUXD1cXUOCfL383RWcHEN83R2VQhwdPZ2dHfVUXD0c1HwdQ3x8HcJVvB3UwgI8ncJdQ7x9PcD8UI8XBWCHX1deRhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGhoZGluYmRiaOhMXGqAHfFLrw</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>WIRING BOARD, ELECTRONIC DEVICE PACKAGE, AND METHODS OF PRODUCTION OF THE SAME</title><source>esp@cenet</source><creator>YOSHIDA HIDEKI ; ISODA SATOSHI ; URASAKI NAOYUKI ; KOTANI HAYATO</creator><creatorcontrib>YOSHIDA HIDEKI ; ISODA SATOSHI ; URASAKI NAOYUKI ; KOTANI HAYATO</creatorcontrib><description>A wiring board which uses both conductor patterns and reflection members provided at gaps therebetween to suppress unevenness in the reflection rate so as to raise the overall reflection rate and provide a reflection function on the surface of the wiring board at the side where an electronic device is mounted; facilitates shaping of the reflection members, controlling of the thickness of the reflection members, and controlling of the surface shape of the reflection members so as to stabilize the reflection rate; and secures close contact between the reflection members and sealing members so as to improve reliability. The wiring board comprises a plurality of wiring layers provided with conductor patterns disposed on base members, and base members which electrically insulate the plurality of wiring layers. At the outermost wiring layer among the plurality of wiring layers, reflection members are formed on the portions of the base member where there are no conductor patterns, the surface of these reflection members and the surface of the conductor patterns are made level and the surface of the conductor patterns are exposed from the reflection members.</description><language>eng</language><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; FREQUENCY-CHANGING ; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC ; GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; NON-LINEAR OPTICS ; OPTICAL ANALOGUE/DIGITAL CONVERTERS ; OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS ; OPTICAL LOGIC ELEMENTS ; OPTICS ; PHYSICS ; PRINTED CIRCUITS ; TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION ; TECHNICAL SUBJECTS COVERED BY FORMER USPC ; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS ; TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF</subject><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20111208&amp;DB=EPODOC&amp;CC=US&amp;NR=2011297424A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25542,76516</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20111208&amp;DB=EPODOC&amp;CC=US&amp;NR=2011297424A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>YOSHIDA HIDEKI</creatorcontrib><creatorcontrib>ISODA SATOSHI</creatorcontrib><creatorcontrib>URASAKI NAOYUKI</creatorcontrib><creatorcontrib>KOTANI HAYATO</creatorcontrib><title>WIRING BOARD, ELECTRONIC DEVICE PACKAGE, AND METHODS OF PRODUCTION OF THE SAME</title><description>A wiring board which uses both conductor patterns and reflection members provided at gaps therebetween to suppress unevenness in the reflection rate so as to raise the overall reflection rate and provide a reflection function on the surface of the wiring board at the side where an electronic device is mounted; facilitates shaping of the reflection members, controlling of the thickness of the reflection members, and controlling of the surface shape of the reflection members so as to stabilize the reflection rate; and secures close contact between the reflection members and sealing members so as to improve reliability. The wiring board comprises a plurality of wiring layers provided with conductor patterns disposed on base members, and base members which electrically insulate the plurality of wiring layers. At the outermost wiring layer among the plurality of wiring layers, reflection members are formed on the portions of the base member where there are no conductor patterns, the surface of these reflection members and the surface of the conductor patterns are made level and the surface of the conductor patterns are exposed from the reflection members.</description><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>FREQUENCY-CHANGING</subject><subject>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</subject><subject>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>NON-LINEAR OPTICS</subject><subject>OPTICAL ANALOGUE/DIGITAL CONVERTERS</subject><subject>OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS</subject><subject>OPTICAL LOGIC ELEMENTS</subject><subject>OPTICS</subject><subject>PHYSICS</subject><subject>PRINTED CIRCUITS</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC</subject><subject>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</subject><subject>TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNrjZPAL9wzy9HNXcPJ3DHLRUXD1cXUOCfL383RWcHEN83R2VQhwdPZ2dHfVUXD0c1HwdQ3x8HcJVvB3UwgI8ncJdQ7x9PcD8UI8XBWCHX1deRhY0xJzilN5oTQ3g7Kba4izh25qQX58anFBYnJqXmpJfGiwkYGhoZGluYmRiaOhMXGqAHfFLrw</recordid><startdate>20111208</startdate><enddate>20111208</enddate><creator>YOSHIDA HIDEKI</creator><creator>ISODA SATOSHI</creator><creator>URASAKI NAOYUKI</creator><creator>KOTANI HAYATO</creator><scope>EVB</scope></search><sort><creationdate>20111208</creationdate><title>WIRING BOARD, ELECTRONIC DEVICE PACKAGE, AND METHODS OF PRODUCTION OF THE SAME</title><author>YOSHIDA HIDEKI ; ISODA SATOSHI ; URASAKI NAOYUKI ; KOTANI HAYATO</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2011297424A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>FREQUENCY-CHANGING</topic><topic>GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC</topic><topic>GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>NON-LINEAR OPTICS</topic><topic>OPTICAL ANALOGUE/DIGITAL CONVERTERS</topic><topic>OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS</topic><topic>OPTICAL LOGIC ELEMENTS</topic><topic>OPTICS</topic><topic>PHYSICS</topic><topic>PRINTED CIRCUITS</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC</topic><topic>TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS</topic><topic>TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF</topic><toplevel>online_resources</toplevel><creatorcontrib>YOSHIDA HIDEKI</creatorcontrib><creatorcontrib>ISODA SATOSHI</creatorcontrib><creatorcontrib>URASAKI NAOYUKI</creatorcontrib><creatorcontrib>KOTANI HAYATO</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>YOSHIDA HIDEKI</au><au>ISODA SATOSHI</au><au>URASAKI NAOYUKI</au><au>KOTANI HAYATO</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>WIRING BOARD, ELECTRONIC DEVICE PACKAGE, AND METHODS OF PRODUCTION OF THE SAME</title><date>2011-12-08</date><risdate>2011</risdate><abstract>A wiring board which uses both conductor patterns and reflection members provided at gaps therebetween to suppress unevenness in the reflection rate so as to raise the overall reflection rate and provide a reflection function on the surface of the wiring board at the side where an electronic device is mounted; facilitates shaping of the reflection members, controlling of the thickness of the reflection members, and controlling of the surface shape of the reflection members so as to stabilize the reflection rate; and secures close contact between the reflection members and sealing members so as to improve reliability. The wiring board comprises a plurality of wiring layers provided with conductor patterns disposed on base members, and base members which electrically insulate the plurality of wiring layers. At the outermost wiring layer among the plurality of wiring layers, reflection members are formed on the portions of the base member where there are no conductor patterns, the surface of these reflection members and the surface of the conductor patterns are made level and the surface of the conductor patterns are exposed from the reflection members.</abstract><oa>free_for_read</oa></addata></record>
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recordid cdi_epo_espacenet_US2011297424A1
source esp@cenet
subjects CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS
DEVICES OR ARRANGEMENTS, THE OPTICAL OPERATION OF WHICH ISMODIFIED BY CHANGING THE OPTICAL PROPERTIES OF THE MEDIUM OF THEDEVICES OR ARRANGEMENTS FOR THE CONTROL OF THE INTENSITY,COLOUR, PHASE, POLARISATION OR DIRECTION OF LIGHT, e.g.SWITCHING, GATING, MODULATING OR DEMODULATING
ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
ELECTRICITY
FREQUENCY-CHANGING
GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC
GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS
MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
NON-LINEAR OPTICS
OPTICAL ANALOGUE/DIGITAL CONVERTERS
OPTICAL ELEMENTS, SYSTEMS, OR APPARATUS
OPTICAL LOGIC ELEMENTS
OPTICS
PHYSICS
PRINTED CIRCUITS
TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
TECHNICAL SUBJECTS COVERED BY FORMER USPC
TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
TECHNIQUES OR PROCEDURES FOR THE OPERATION THEREOF
title WIRING BOARD, ELECTRONIC DEVICE PACKAGE, AND METHODS OF PRODUCTION OF THE SAME
url https://sfx.bib-bvb.de/sfx_tum?ctx_ver=Z39.88-2004&ctx_enc=info:ofi/enc:UTF-8&ctx_tim=2025-02-16T12%3A10%3A53IST&url_ver=Z39.88-2004&url_ctx_fmt=infofi/fmt:kev:mtx:ctx&rfr_id=info:sid/primo.exlibrisgroup.com:primo3-Article-epo_EVB&rft_val_fmt=info:ofi/fmt:kev:mtx:patent&rft.genre=patent&rft.au=YOSHIDA%20HIDEKI&rft.date=2011-12-08&rft_id=info:doi/&rft_dat=%3Cepo_EVB%3EUS2011297424A1%3C/epo_EVB%3E%3Curl%3E%3C/url%3E&disable_directlink=true&sfx.directlink=off&sfx.report_link=0&rft_id=info:oai/&rft_id=info:pmid/&rfr_iscdi=true