First-level interconnects with slender columns, and processes of forming same
A column is coupled to a last metallization of a die and the column is mated to a mounting substrate with that aid of a solder. The column may have the solder attached thereto before mating to the mounting substrate and the mounting substrate may be a bare-board (no solder mask) during the mating pr...
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creator | GANESAN SANKA HARRIES RICHARD J SHARAN SUJIT |
description | A column is coupled to a last metallization of a die and the column is mated to a mounting substrate with that aid of a solder. The column may have the solder attached thereto before mating to the mounting substrate and the mounting substrate may be a bare-board (no solder mask) during the mating process. The column has an aspect ratio between 0.75 and 10. |
format | Patent |
fullrecord | <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2011122592A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2011122592A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2011122592A13</originalsourceid><addsrcrecordid>eNqNyjEKAjEQBdA0FqLeYcDWBROxsBRxsbFS6yVkf9ZAMgmZqNe38QBWr3lzde1DldZFvBEpcEN1mRmuCX1Ce5JE8IhKLsdXYtmQ5ZFKzQ4iEMqefK4p8ERiE5Zq5m0UrH4u1Lo_30-XDiUPkGIdGG143MxWa23M_mCOevff-gLeoTdT</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>First-level interconnects with slender columns, and processes of forming same</title><source>esp@cenet</source><creator>GANESAN SANKA ; HARRIES RICHARD J ; SHARAN SUJIT</creator><creatorcontrib>GANESAN SANKA ; HARRIES RICHARD J ; SHARAN SUJIT</creatorcontrib><description>A column is coupled to a last metallization of a die and the column is mated to a mounting substrate with that aid of a solder. The column may have the solder attached thereto before mating to the mounting substrate and the mounting substrate may be a bare-board (no solder mask) during the mating process. The column has an aspect ratio between 0.75 and 10.</description><language>eng</language><subject>BASIC ELECTRIC ELEMENTS ; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ; ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ; ELECTRICITY ; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS ; PRINTED CIRCUITS ; SEMICONDUCTOR DEVICES</subject><creationdate>2011</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20110526&DB=EPODOC&CC=US&NR=2011122592A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,776,881,25544,76293</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&date=20110526&DB=EPODOC&CC=US&NR=2011122592A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GANESAN SANKA</creatorcontrib><creatorcontrib>HARRIES RICHARD J</creatorcontrib><creatorcontrib>SHARAN SUJIT</creatorcontrib><title>First-level interconnects with slender columns, and processes of forming same</title><description>A column is coupled to a last metallization of a die and the column is mated to a mounting substrate with that aid of a solder. The column may have the solder attached thereto before mating to the mounting substrate and the mounting substrate may be a bare-board (no solder mask) during the mating process. The column has an aspect ratio between 0.75 and 10.</description><subject>BASIC ELECTRIC ELEMENTS</subject><subject>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</subject><subject>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</subject><subject>ELECTRICITY</subject><subject>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</subject><subject>PRINTED CIRCUITS</subject><subject>SEMICONDUCTOR DEVICES</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2011</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNyjEKAjEQBdA0FqLeYcDWBROxsBRxsbFS6yVkf9ZAMgmZqNe38QBWr3lzde1DldZFvBEpcEN1mRmuCX1Ce5JE8IhKLsdXYtmQ5ZFKzQ4iEMqefK4p8ERiE5Zq5m0UrH4u1Lo_30-XDiUPkGIdGG143MxWa23M_mCOevff-gLeoTdT</recordid><startdate>20110526</startdate><enddate>20110526</enddate><creator>GANESAN SANKA</creator><creator>HARRIES RICHARD J</creator><creator>SHARAN SUJIT</creator><scope>EVB</scope></search><sort><creationdate>20110526</creationdate><title>First-level interconnects with slender columns, and processes of forming same</title><author>GANESAN SANKA ; HARRIES RICHARD J ; SHARAN SUJIT</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2011122592A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2011</creationdate><topic>BASIC ELECTRIC ELEMENTS</topic><topic>CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS</topic><topic>ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR</topic><topic>ELECTRICITY</topic><topic>MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS</topic><topic>PRINTED CIRCUITS</topic><topic>SEMICONDUCTOR DEVICES</topic><toplevel>online_resources</toplevel><creatorcontrib>GANESAN SANKA</creatorcontrib><creatorcontrib>HARRIES RICHARD J</creatorcontrib><creatorcontrib>SHARAN SUJIT</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GANESAN SANKA</au><au>HARRIES RICHARD J</au><au>SHARAN SUJIT</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>First-level interconnects with slender columns, and processes of forming same</title><date>2011-05-26</date><risdate>2011</risdate><abstract>A column is coupled to a last metallization of a die and the column is mated to a mounting substrate with that aid of a solder. The column may have the solder attached thereto before mating to the mounting substrate and the mounting substrate may be a bare-board (no solder mask) during the mating process. The column has an aspect ratio between 0.75 and 10.</abstract><oa>free_for_read</oa></addata></record> |
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subjects | BASIC ELECTRIC ELEMENTS CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR ELECTRICITY MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS PRINTED CIRCUITS SEMICONDUCTOR DEVICES |
title | First-level interconnects with slender columns, and processes of forming same |
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