MEMORY TEST CIRCUIT, SEMICONDUCTOR INTEGRATED CIRCUIT AND MEMORY TEST METHOD

A memory test circuit tests a memory including an actual array portion and a redundancy portion. The memory test circuit includes: an input data selector outputting first test data excluding data for the redundancy portion in test data representing data for the actual array portion and the redundanc...

Ausführliche Beschreibung

Bibliographische Detailangaben

1. Verfasser:	KUDOU KAZUYA
Format:	Patent
Sprache:	eng
Schlagworte:	INFORMATION STORAGE PHYSICS STATIC STORES
Online-Zugang:	Volltext bestellen
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