WAIT LOSS SYNCHRONIZATION

Synchronizing threads on loss of memory access monitoring. Using a processor level instruction included as part of an instruction set architecture for a processor, a read, or write monitor to detect writes, or reads or writes respectively from other agents on a first set of one or more memory locati...

Ausführliche Beschreibung

Bibliographische Detailangaben

Hauptverfasser:	ADL-TABATABAI ALI-REZA, CALLAHAN DAVID, SHEAFFER GAD, SAHA BRATIN, GRAY JAN, SMITH BURTON JORDAN
Format:	Patent
Sprache:	eng
Schlagworte:	CALCULATING COMPUTING COUNTING ELECTRIC DIGITAL DATA PROCESSING PHYSICS
Online-Zugang:	Volltext bestellen
Tags:	Tag hinzufügen Keine Tags, Fügen Sie den ersten Tag hinzu!