INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS IN A DUAL-BANK CACHE WITH SINGLE DISPATCH INTO WRITE/READ DATA FLOW

An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The...

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Hauptverfasser: GUTHRIE GUY LYNN, STARKE WILLIAM JOHN, GHAI SANJEEV, SHEN HUGH
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creator GUTHRIE GUY LYNN
STARKE WILLIAM JOHN
GHAI SANJEEV
SHEN HUGH
description An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.
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fullrecord <record><control><sourceid>epo_EVB</sourceid><recordid>TN_cdi_epo_espacenet_US2010268890A1</recordid><sourceformat>XML</sourceformat><sourcesystem>PC</sourcesystem><sourcerecordid>US2010268890A1</sourcerecordid><originalsourceid>FETCH-epo_espacenet_US2010268890A13</originalsourceid><addsrcrecordid>eNqNjEEKwjAQAHvxIOofFjwXWwWpx7XZ2sU0KUlK8VSKxJNooT7DRxuqD_A0l5mZR29WhTYVOtYKSlRCsjqBvVhHFbTsSuCqIsHoCGxekmgmQRcgNQrQNZmptcAKEESDMj6iOkOOwf4ebCgkgWBbo8vDUTkNrWFHG0NhItAhFFK3y2h26--jX_24iNYFhSL2w7Pz49Bf_cO_usZukzTZ7rPskGC6-8_6ACBfP_Q</addsrcrecordid><sourcetype>Open Access Repository</sourcetype><iscdi>true</iscdi><recordtype>patent</recordtype></control><display><type>patent</type><title>INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS IN A DUAL-BANK CACHE WITH SINGLE DISPATCH INTO WRITE/READ DATA FLOW</title><source>esp@cenet</source><creator>GUTHRIE GUY LYNN ; STARKE WILLIAM JOHN ; GHAI SANJEEV ; SHEN HUGH</creator><creatorcontrib>GUTHRIE GUY LYNN ; STARKE WILLIAM JOHN ; GHAI SANJEEV ; SHEN HUGH</creatorcontrib><description>An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.</description><language>eng</language><subject>CALCULATING ; COMPUTING ; COUNTING ; ELECTRIC DIGITAL DATA PROCESSING ; PHYSICS</subject><creationdate>2010</creationdate><oa>free_for_read</oa><woscitedreferencessubscribed>false</woscitedreferencessubscribed></display><links><openurl>$$Topenurl_article</openurl><openurlfulltext>$$Topenurlfull_article</openurlfulltext><thumbnail>$$Tsyndetics_thumb_exl</thumbnail><linktohtml>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20101021&amp;DB=EPODOC&amp;CC=US&amp;NR=2010268890A1$$EHTML$$P50$$Gepo$$Hfree_for_read</linktohtml><link.rule.ids>230,308,780,885,25564,76547</link.rule.ids><linktorsrc>$$Uhttps://worldwide.espacenet.com/publicationDetails/biblio?FT=D&amp;date=20101021&amp;DB=EPODOC&amp;CC=US&amp;NR=2010268890A1$$EView_record_in_European_Patent_Office$$FView_record_in_$$GEuropean_Patent_Office$$Hfree_for_read</linktorsrc></links><search><creatorcontrib>GUTHRIE GUY LYNN</creatorcontrib><creatorcontrib>STARKE WILLIAM JOHN</creatorcontrib><creatorcontrib>GHAI SANJEEV</creatorcontrib><creatorcontrib>SHEN HUGH</creatorcontrib><title>INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS IN A DUAL-BANK CACHE WITH SINGLE DISPATCH INTO WRITE/READ DATA FLOW</title><description>An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.</description><subject>CALCULATING</subject><subject>COMPUTING</subject><subject>COUNTING</subject><subject>ELECTRIC DIGITAL DATA PROCESSING</subject><subject>PHYSICS</subject><fulltext>true</fulltext><rsrctype>patent</rsrctype><creationdate>2010</creationdate><recordtype>patent</recordtype><sourceid>EVB</sourceid><recordid>eNqNjEEKwjAQAHvxIOofFjwXWwWpx7XZ2sU0KUlK8VSKxJNooT7DRxuqD_A0l5mZR29WhTYVOtYKSlRCsjqBvVhHFbTsSuCqIsHoCGxekmgmQRcgNQrQNZmptcAKEESDMj6iOkOOwf4ebCgkgWBbo8vDUTkNrWFHG0NhItAhFFK3y2h26--jX_24iNYFhSL2w7Pz49Bf_cO_usZukzTZ7rPskGC6-8_6ACBfP_Q</recordid><startdate>20101021</startdate><enddate>20101021</enddate><creator>GUTHRIE GUY LYNN</creator><creator>STARKE WILLIAM JOHN</creator><creator>GHAI SANJEEV</creator><creator>SHEN HUGH</creator><scope>EVB</scope></search><sort><creationdate>20101021</creationdate><title>INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS IN A DUAL-BANK CACHE WITH SINGLE DISPATCH INTO WRITE/READ DATA FLOW</title><author>GUTHRIE GUY LYNN ; STARKE WILLIAM JOHN ; GHAI SANJEEV ; SHEN HUGH</author></sort><facets><frbrtype>5</frbrtype><frbrgroupid>cdi_FETCH-epo_espacenet_US2010268890A13</frbrgroupid><rsrctype>patents</rsrctype><prefilter>patents</prefilter><language>eng</language><creationdate>2010</creationdate><topic>CALCULATING</topic><topic>COMPUTING</topic><topic>COUNTING</topic><topic>ELECTRIC DIGITAL DATA PROCESSING</topic><topic>PHYSICS</topic><toplevel>online_resources</toplevel><creatorcontrib>GUTHRIE GUY LYNN</creatorcontrib><creatorcontrib>STARKE WILLIAM JOHN</creatorcontrib><creatorcontrib>GHAI SANJEEV</creatorcontrib><creatorcontrib>SHEN HUGH</creatorcontrib><collection>esp@cenet</collection></facets><delivery><delcategory>Remote Search Resource</delcategory><fulltext>fulltext_linktorsrc</fulltext></delivery><addata><au>GUTHRIE GUY LYNN</au><au>STARKE WILLIAM JOHN</au><au>GHAI SANJEEV</au><au>SHEN HUGH</au><format>patent</format><genre>patent</genre><ristype>GEN</ristype><title>INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS IN A DUAL-BANK CACHE WITH SINGLE DISPATCH INTO WRITE/READ DATA FLOW</title><date>2010-10-21</date><risdate>2010</risdate><abstract>An information handling system (IHS) includes a processor with a cache memory system. The processor includes a processor core with an L1 cache memory that couples to an L2 cache memory. The processor includes an arbitration mechanism that controls load and store requests to the L2 cache memory. The arbitration mechanism includes control logic that enables a load request to interrupt a store request that the L2 cache memory is currently servicing. The L2 cache memory includes dual data banks so that one bank may perform a load operation while the other bank performs a store operation. The cache system provides a single dispatch point into the data flow to the dual cache banks of the L2 cache memory.</abstract><oa>free_for_read</oa></addata></record>
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subjects CALCULATING
COMPUTING
COUNTING
ELECTRIC DIGITAL DATA PROCESSING
PHYSICS
title INFORMATION HANDLING SYSTEM WITH IMMEDIATE SCHEDULING OF LOAD OPERATIONS IN A DUAL-BANK CACHE WITH SINGLE DISPATCH INTO WRITE/READ DATA FLOW
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